Home
last modified time | relevance | path

Searched refs:mmDP1_DP_VID_INTERRUPT_CNTL (Results 1 – 14 of 14) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dce/
H A Ddce_6_0_d.h3213 #define mmDP1_DP_VID_INTERRUPT_CNTL 0x1FCF macro
H A Ddce_8_0_d.h3861 #define mmDP1_DP_VID_INTERRUPT_CNTL 0x1fcf macro
H A Ddce_10_0_d.h4493 #define mmDP1_DP_VID_INTERRUPT_CNTL 0x4bae macro
H A Ddce_11_0_d.h4469 #define mmDP1_DP_VID_INTERRUPT_CNTL 0x4bae macro
H A Ddce_11_2_d.h5701 #define mmDP1_DP_VID_INTERRUPT_CNTL 0x4bae macro
H A Ddce_12_0_offset.h10506 #define mmDP1_DP_VID_INTERRUPT_CNTL … macro
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_2_0_3_offset.h5810 #define mmDP1_DP_VID_INTERRUPT_CNTL … macro
H A Ddcn_3_0_3_offset.h5319 #define mmDP1_DP_VID_INTERRUPT_CNTL … macro
H A Ddcn_3_0_1_offset.h8286 #define mmDP1_DP_VID_INTERRUPT_CNTL … macro
H A Ddcn_1_0_offset.h8685 #define mmDP1_DP_VID_INTERRUPT_CNTL … macro
H A Ddcn_2_1_0_offset.h10209 #define mmDP1_DP_VID_INTERRUPT_CNTL … macro
H A Ddcn_3_0_2_offset.h9901 #define mmDP1_DP_VID_INTERRUPT_CNTL … macro
H A Ddcn_2_0_0_offset.h11300 #define mmDP1_DP_VID_INTERRUPT_CNTL … macro
H A Ddcn_3_0_0_offset.h11037 #define mmDP1_DP_VID_INTERRUPT_CNTL … macro