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Searched refs:fdiv (Results 1 – 25 of 35) sorted by relevance

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/openbmc/u-boot/arch/mips/mach-mt7620/
H A Dddr_calibrate.c145 u32 fdiv = 0, frac = 0; in ddr_calibrate() local
149 fdiv = (u32)((val >> 8) & 0x0F); in ddr_calibrate()
155 while (frac < fdiv) { in ddr_calibrate()
157 fdiv = (val >> 8) & 0x0f; in ddr_calibrate()
158 fdiv--; in ddr_calibrate()
160 val |= (fdiv << 8); in ddr_calibrate()
164 fdiv = (val >> 8) & 0x0f; in ddr_calibrate()
/openbmc/linux/drivers/spi/
H A Dspi-xlp.c138 u32 fdiv, cfg; in xlp_spi_setup() local
146 fdiv = DIV_ROUND_UP(xspi->spi_clk, spi->max_speed_hz); in xlp_spi_setup()
147 if (fdiv > XLP_SPI_FDIV_MAX) in xlp_spi_setup()
148 fdiv = XLP_SPI_FDIV_MAX; in xlp_spi_setup()
149 else if (fdiv < XLP_SPI_FDIV_MIN) in xlp_spi_setup()
150 fdiv = XLP_SPI_FDIV_MIN; in xlp_spi_setup()
152 xlp_spi_reg_write(xspi, cs, XLP_SPI_FDIV, fdiv); in xlp_spi_setup()
173 if (fdiv == 4) in xlp_spi_setup()
/openbmc/u-boot/drivers/clk/mediatek/
H A Dclk-mtk.c258 static ulong mtk_factor_recalc_rate(const struct mtk_fixed_factor *fdiv, in mtk_factor_recalc_rate() argument
261 u64 rate = parent_rate * fdiv->mult; in mtk_factor_recalc_rate()
263 do_div(rate, fdiv->div); in mtk_factor_recalc_rate()
271 const struct mtk_fixed_factor *fdiv = &priv->tree->fdivs[off]; in mtk_topckgen_get_factor_rate() local
274 switch (fdiv->flags & CLK_PARENT_MASK) { in mtk_topckgen_get_factor_rate()
276 rate = mtk_clk_find_parent_rate(clk, fdiv->parent, in mtk_topckgen_get_factor_rate()
280 rate = mtk_clk_find_parent_rate(clk, fdiv->parent, NULL); in mtk_topckgen_get_factor_rate()
287 return mtk_factor_recalc_rate(fdiv, rate); in mtk_topckgen_get_factor_rate()
/openbmc/linux/drivers/media/tuners/
H A Dit913x.c20 u8 fdiv; member
53 dev->fdiv = 3; in it913x_init()
60 dev->fdiv = 1; in it913x_init()
95 dev->fn_min /= (dev->fdiv * nv_val); in it913x_init()
274 t_cal_freq = (c->frequency / 1000) * n_div * dev->fdiv; in it913x_set_params()
/openbmc/linux/drivers/tty/serial/
H A Dmax310x.c599 unsigned long fdiv, fmul, bestfreq = freq; in max310x_set_ref_clk() local
606 fdiv = DIV_ROUND_CLOSEST(freq, div); in max310x_set_ref_clk()
609 fmul = fdiv * 6; in max310x_set_ref_clk()
610 if ((fdiv >= 500000) && (fdiv <= 800000)) in max310x_set_ref_clk()
616 fmul = fdiv * 48; in max310x_set_ref_clk()
617 if ((fdiv >= 850000) && (fdiv <= 1200000)) in max310x_set_ref_clk()
623 fmul = fdiv * 96; in max310x_set_ref_clk()
624 if ((fdiv >= 425000) && (fdiv <= 1000000)) in max310x_set_ref_clk()
630 fmul = fdiv * 144; in max310x_set_ref_clk()
631 if ((fdiv >= 390000) && (fdiv <= 667000)) in max310x_set_ref_clk()
/openbmc/linux/arch/mips/ath25/
H A Dar2315.c207 unsigned int pllc_out, refdiv, fdiv, divby2; in ar2315_sys_clk() local
213 fdiv = ATH25_REG_MS(pllc_ctrl, AR2315_PLLC_FDBACK_DIV); in ar2315_sys_clk()
215 pllc_out = (40000000 / refdiv) * (2 * divby2) * fdiv; in ar2315_sys_clk()
/openbmc/linux/drivers/clk/st/
H A Dclk-flexgen.c43 struct clk_divider fdiv; member
144 struct clk_hw *fdiv_hw = &flexgen->fdiv.hw; in flexgen_recalc_rate()
160 struct clk_hw *fdiv_hw = &flexgen->fdiv.hw; in flexgen_set_rate()
254 fgxbar->fdiv.lock = lock; in clk_register_flexgen()
255 fgxbar->fdiv.reg = fdiv_reg; in clk_register_flexgen()
256 fgxbar->fdiv.width = 6; in clk_register_flexgen()
/openbmc/linux/drivers/clk/socfpga/
H A Dclk-pll-s10.c44 unsigned long fdiv, reg, rdiv, qdiv; in n5x_clk_pll_recalc_rate() local
49 fdiv = (reg & SOCFPGA_N5X_PLLDIV_FDIV_MASK) >> SOCFPGA_N5X_PLLDIV_FDIV_SHIFT; in n5x_clk_pll_recalc_rate()
58 return ((parent_rate * 2 * (fdiv + 1)) / ((rdiv + 1) * power)); in n5x_clk_pll_recalc_rate()
/openbmc/linux/drivers/clk/bcm/
H A Dclk-bcm2835.c549 u32 *ndiv, u32 *fdiv) in bcm2835_pll_choose_ndiv_and_fdiv() argument
557 *fdiv = div & ((1 << A2W_PLL_FRAC_BITS) - 1); in bcm2835_pll_choose_ndiv_and_fdiv()
561 u32 ndiv, u32 fdiv, u32 pdiv) in bcm2835_pll_rate_from_divisors() argument
568 rate = (u64)parent_rate * ((ndiv << A2W_PLL_FRAC_BITS) + fdiv); in bcm2835_pll_rate_from_divisors()
578 u32 ndiv, fdiv; in bcm2835_pll_round_rate() local
594 u32 ndiv, pdiv, fdiv; in bcm2835_pll_get_rate() local
600 fdiv = cprman_read(cprman, data->frac_reg) & A2W_PLL_FRAC_MASK; in bcm2835_pll_get_rate()
608 fdiv *= 2; in bcm2835_pll_get_rate()
689 u32 ndiv, fdiv, a2w_ctl; in bcm2835_pll_set_rate() local
700 bcm2835_pll_choose_ndiv_and_fdiv(rate, parent_rate, &ndiv, &fdiv); in bcm2835_pll_set_rate()
[all …]
/openbmc/linux/arch/powerpc/math-emu/
H A Dfdiv.c11 fdiv(void *frD, void *frA, void *frB) in fdiv() function
H A DMakefile6 fctiwz.o fdiv.o fdivs.o fmadd.o \
H A Dmath.c34 FLOATFUNC(fdiv);
287 case FDIV: func = fdiv; type = AB; break; in do_mathemu()
/openbmc/qemu/target/rx/
H A Dhelper.h10 DEF_HELPER_FLAGS_3(fdiv, TCG_CALL_NO_WG, f32, env, f32, f32)
H A Dop_helper.c153 FLOATOP(fdiv, float32_div) in FLOATOP()
/openbmc/qemu/hw/misc/
H A Dbcm2835_cprman.c75 uint64_t freq, ndiv, fdiv, pdiv; in pll_update() local
90 fdiv = FIELD_EX32(*pll->reg_a2w_frac, A2W_PLLx_FRAC, FRAC); in pll_update()
95 fdiv *= 2; in pll_update()
103 ((ndiv << R_A2W_PLLx_FRAC_FRAC_LENGTH) + fdiv); in pll_update()
/openbmc/qemu/target/microblaze/
H A Dhelper.h9 DEF_HELPER_FLAGS_3(fdiv, TCG_CALL_NO_WG, i32, env, i32, i32)
H A Dinsns.decode146 fdiv 010110 ..... ..... ..... 0011 000 0000 @typea
/openbmc/linux/arch/m68k/ifpsp060/
H A DMISC69 fdiv.s : 2.5
128 fdiv.s : 2.5
H A Dfplsp.doc124 The fabs/fadd/fdiv/fint/fintrz/fmul/fneg/fsqrt/fsub entry points
/openbmc/linux/Documentation/arch/arm/vfp/
H A Drelease-notes.rst21 - fdiv
/openbmc/linux/arch/powerpc/include/asm/
H A Dkvm_fpu.h60 FPD_TWO_IN(fdiv)
/openbmc/linux/arch/powerpc/kvm/
H A Dfpu.S262 FPD_TWO_IN(fdiv)
/openbmc/linux/arch/sh/math-emu/
H A Dmath.c127 fdiv(struct sh_fpu_soft_struct *fregs, struct pt_regs *regs, int m, int n) in fdiv() function
397 fadd, fsub, fmul, fdiv, fcmp_eq, fcmp_gt, fmov_idx_reg, fmov_reg_idx,
/openbmc/qemu/target/m68k/
H A Dhelper.h52 DEF_HELPER_4(fdiv, void, env, fp, fp, fp)
/openbmc/qemu/target/tricore/
H A Dhelper.h108 DEF_HELPER_3(fdiv, i32, env, i32, i32)

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