/openbmc/qemu/target/hexagon/imported/ |
H A D | subinsns.idef | 65 …2)", ATTRIBS(A_REGWRSIZE_4B,A_MEMSIZE_4B,A_LOAD,A_SUBINSN),"load word", {fEA_RI(RsV,uiV); fLOAD(1,… 66 …:0)",ATTRIBS(A_MEMSIZE_1B,A_LOAD,A_SUBINSN,A_REGWRSIZE_1B),"load byte", {fEA_RI(RsV,uiV); fLOAD(1,… 68 …1)", ATTRIBS(A_REGWRSIZE_2B,A_MEMSIZE_2B,A_LOAD,A_SUBINSN),"load half", {fEA_RI(RsV,uiV); fLOAD(1,… 69 …:1)",ATTRIBS(A_REGWRSIZE_2B,A_MEMSIZE_2B,A_LOAD,A_SUBINSN),"load half", {fEA_RI(RsV,uiV); fLOAD(1,… 70 …=memb(Rs16+#u3:0)", ATTRIBS(A_MEMSIZE_1B,A_LOAD,A_SUBINSN),"load byte", {fEA_RI(RsV,uiV); fLOAD(1,… 71 …)", ATTRIBS(A_REGWRSIZE_4B,A_MEMSIZE_4B,A_LOAD,A_SUBINSN),"load word", {fEA_RI(fREAD_SP(),uiV); f… 137 …, ATTRIBS(A_REGWRSIZE_4B,A_MEMSIZE_4B,A_STORE,A_SUBINSN), "store word", {fEA_RI(RsV,uiV); fSTORE(1… 138 …16+#u4:0)=Rt16", ATTRIBS(A_MEMSIZE_1B,A_STORE,A_SUBINSN), "store byte", {fEA_RI(RsV,uiV); fSTORE(1… 139 …16+#u3:1)=Rt16", ATTRIBS(A_MEMSIZE_2B,A_STORE,A_SUBINSN), "store half", {fEA_RI(RsV,uiV); fSTORE(1… 143 …0)=#0", ATTRIBS(A_MEMSIZE_1B,A_STORE,A_SUBINSN,A_ROPS_2), "store byte", {fEA_RI(RsV,uiV); fSTORE(1… [all …]
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H A D | ldst.idef | 24 Q6INSN(L2_##TAG##_io, OPER"(Rs32+#s11:"SHFT")", ATTRIB,DESCR,{fIMMEXT(siV); fEA_RI(RsV,si… 105 Q6INSN(S2_##TAG##_io, OPER"(Rs32+#s11:"SHFT")="DEST, ATTRIB,DESCR,{fIMMEXT(siV); fEA_RI(RsV,si… 127 { fEA_RI(RxV,-8); fSTORE(1,8,EA,fFRAME_SCRAMBLE((fCAST8_8u(fREAD_LR()) << 32) | fCAST4_4u(fREAD_FP(… 221 …f (Pt4) "OPER"(Rs32+#u6:"SHFT")", ATTRIB,DESCR,{fIMMEXT(uiV); fEA_RI(RsV,uiV); if(fLSBO… 225 Q6INSN(L2_p##TAG##tnew_io,"if (Pt4.new) "OPER"(Rs32+#u6:"SHFT")",ATTRIB,DESCR,{fIMMEXT(uiV); fEA_RI… 226 …w_io,"if (!Pt4.new) "OPER"(Rs32+#u6:"SHFT")",ATTRIB,DESCR,{fIMMEXT(uiV); fEA_RI(RsV,uiV); if (fLSB… 317 Q6INSN(S4_##TAG##t_io,"if (Pv4) "OPER"(Rs32+#u6:"SHFT")="DEST,ATTRIB,DESCR,{fEA_RI(RsV,uiV); if (fL… 318 Q6INSN(S4_##TAG##f_io,"if (!Pv4) "OPER"(Rs32+#u6:"SHFT")="DEST,ATTRIB,DESCR,{fEA_RI(RsV,uiV); if (f… 319 Q6INSN(S4_##TAG##tnew_io,"if (Pv4.new) "OPER"(Rs32+#u6:"SHFT")="DEST,ATTRIB,DESCR,{fEA_RI(RsV,uiV);… 320 Q6INSN(S4_##TAG##fnew_io,"if (!Pv4.new) "OPER"(Rs32+#u6:"SHFT")="DEST,ATTRIB,DESCR,{fEA_RI(RsV,uiV)… [all …]
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H A D | system.idef | 43 …u11:3)",ATTRIBS(A_RESTRICT_PREFERSLOT0,A_DCFETCH),"Data Cache Prefetch",{fEA_RI(RsV,uiV); fDCFETCH…
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H A D | macros.def | 869 fEA_RI, /* Calculate EA with Register + Immediate Offset */
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/openbmc/qemu/target/hexagon/ |
H A D | gen_tcg_hvx.h | 626 fEA_RI(RtV, siV * sizeof(MMVector)), \ 631 fEA_RI(RtV, siV * sizeof(MMVector)), \ 724 fGEN_TCG_NEWVAL_VEC_STORE(fEA_RI(RtV, siV * sizeof(MMVector)), \ 797 fEA_RI(RtV, siV * sizeof(MMVector)), \ 802 fEA_RI(RtV, siV * sizeof(MMVector)), \ 807 fEA_RI(RtV, siV * sizeof(MMVector)), \ 812 fEA_RI(RtV, siV * sizeof(MMVector)), \
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H A D | gen_tcg.h | 171 fGEN_TCG_loadbXw2(fEA_RI(RsV, siV), false) 175 fGEN_TCG_loadbXw2(fEA_RI(RsV, siV), true) 223 fGEN_TCG_loadbXw4(fEA_RI(RsV, siV), false) 227 fGEN_TCG_loadbXw4(fEA_RI(RsV, siV), true) 274 fGEN_TCG_loadalignh(fEA_RI(RsV, siV)) 301 fGEN_TCG_loadalignb(fEA_RI(RsV, siV))
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H A D | macros.h | 426 #define fEA_RI(REG, IMM) tcg_gen_addi_tl(EA, REG, IMM) macro 439 #define fEA_RI(REG, IMM) \ macro
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/openbmc/qemu/target/hexagon/idef-parser/ |
H A D | macros.inc | 107 #define fEA_RI(REG, IMM) (EA = REG + IMM)
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/openbmc/qemu/target/hexagon/imported/mmvec/ |
H A D | ext.idef | 236 EXTINSN(V6_##TAG##_ai, SYNTAXA "(Rt32+#s4)" NT SYNTAXB,ATTRIB,DESCR,{ fEA_RI(RtV,VEC_SCALE(siV… 242 …AXA "(Rt32+#s4)" NT SYNTAXB, ATTRIB,DESCR, { if (fLSBOLD(SYNTAXP##V)) { fEA_RI(RtV,siV*fVECSIZE()… 247 …XA "(Rt32+#s4)" NT SYNTAXB,ATTRIB,DESCR, { if (fLSBOLDNOT(SYNTAXP##V)) { fEA_RI(RtV,siV*fVECSIZE()…
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