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Searched refs:ddrclk (Results 1 – 6 of 6) sorted by relevance

/openbmc/linux/drivers/clk/rockchip/
H A Dclk-ddr.c76 val = readl(ddrclk->reg_base + in rockchip_ddrclk_get_parent()
77 ddrclk->mux_offset) >> ddrclk->mux_shift; in rockchip_ddrclk_get_parent()
102 ddrclk = kzalloc(sizeof(*ddrclk), GFP_KERNEL); in rockchip_clk_register_ddrclk()
103 if (!ddrclk) in rockchip_clk_register_ddrclk()
119 kfree(ddrclk); in rockchip_clk_register_ddrclk()
123 ddrclk->reg_base = reg_base; in rockchip_clk_register_ddrclk()
124 ddrclk->lock = lock; in rockchip_clk_register_ddrclk()
125 ddrclk->hw.init = &init; in rockchip_clk_register_ddrclk()
127 ddrclk->mux_shift = mux_shift; in rockchip_clk_register_ddrclk()
131 ddrclk->ddr_flag = ddr_flag; in rockchip_clk_register_ddrclk()
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/openbmc/linux/Documentation/devicetree/bindings/arm/marvell/
H A Dkirkwood.txt12 cpus/cpu@0 with three clocks, "cpu_clk", "ddrclk" and "powersave",
14 between the "cpu_clk" and the "ddrclk".
26 clock-names = "cpu_clk", "ddrclk", "powersave";
/openbmc/linux/Documentation/devicetree/bindings/clock/
H A Dmvebu-core-clock.txt18 3 = ddrclk (DDR clock)
24 3 = ddrclk (DDR clock)
37 2 = ddrclk (DDR clock)
44 3 = ddrclk (DDR controller clock derived from CPU0 clock)
49 2 = ddrclk (DDR controller clock derived from CPU0 clock)
72 output names ("tclk", "cpuclk", "l2clk", "ddrclk")
/openbmc/u-boot/arch/mips/mach-ath79/ar934x/
H A Dclk.c263 u32 cpuclk, ddrclk, busclk; in ar934x_update_clock() local
283 ddrclk = ar934x_get_xtal(); in ar934x_update_clock()
285 ddrclk = ddrpll; in ar934x_update_clock()
287 ddrclk = cpupll; in ar934x_update_clock()
304 gd->mem_clk = ddrclk / (ddrdiv + 1); in ar934x_update_clock()
/openbmc/u-boot/arch/arm/dts/
H A Dkirkwood.dtsi21 clock-names = "cpu_clk", "ddrclk", "powersave";
/openbmc/linux/arch/arm/boot/dts/marvell/
H A Dkirkwood.dtsi22 clock-names = "cpu_clk", "ddrclk", "powersave";