Home
last modified time | relevance | path

Searched refs:core_registers (Results 1 – 2 of 2) sorted by relevance

/openbmc/qemu/hw/display/
H A Dxlnx_dp.c488 return s->core_registers[DP_AUX_ADDRESS]; in xlnx_dp_aux_get_address()
673 flags = s->core_registers[DP_INT_STATUS] & ~s->core_registers[DP_INT_MASK]; in xlnx_dp_update_irq()
727 ret = s->core_registers[DP_INT_MASK]; in xlnx_dp_read()
729 ret = s->core_registers[offset]; in xlnx_dp_read()
784 s->core_registers[offset] = value & 0x01; in xlnx_dp_write()
861 s->core_registers[offset] = 0x00000000; in xlnx_dp_write()
895 s->core_registers[DP_INT_MASK] |= value; in xlnx_dp_write()
900 s->core_registers[offset] = value; in xlnx_dp_write()
1345 memset(s->core_registers, 0, sizeof(s->core_registers)); in xlnx_dp_reset()
1347 s->core_registers[DP_CORE_ID] = 0x01020000; in xlnx_dp_reset()
[all …]
/openbmc/qemu/include/hw/display/
H A Dxlnx_dp.h65 uint32_t core_registers[DP_CORE_REG_ARRAY_SIZE]; member