Lines Matching refs:core_registers
266 VMSTATE_UINT32_ARRAY(core_registers, XlnxDPState,
332 bool activated = ((s->core_registers[DP_TX_AUDIO_CONTROL] in xlnx_dp_audio_activate()
488 return s->core_registers[DP_AUX_ADDRESS]; in xlnx_dp_aux_get_address()
514 s->core_registers[DP_AUX_REPLY_CODE] = aux_request(s->aux_bus, cmd, in xlnx_dp_aux_set_command()
517 s->core_registers[DP_REPLY_DATA_COUNT] = nbytes; in xlnx_dp_aux_set_command()
519 if (s->core_registers[DP_AUX_REPLY_CODE] == AUX_I2C_ACK) { in xlnx_dp_aux_set_command()
529 s->core_registers[DP_AUX_REPLY_CODE] = aux_request(s->aux_bus, cmd, in xlnx_dp_aux_set_command()
542 s->core_registers[DP_INTERRUPT_SIGNAL_STATE] |= 0x04; in xlnx_dp_aux_set_command()
578 uint16_t width = s->core_registers[DP_MAIN_STREAM_HRES]; in xlnx_dp_recreate_surface()
579 uint16_t height = s->core_registers[DP_MAIN_STREAM_VRES]; in xlnx_dp_recreate_surface()
673 flags = s->core_registers[DP_INT_STATUS] & ~s->core_registers[DP_INT_MASK]; in xlnx_dp_update_irq()
688 ret = s->core_registers[DP_TX_USER_FIFO_OVERFLOW]; in xlnx_dp_read()
689 s->core_registers[DP_TX_USER_FIFO_OVERFLOW] = 0; in xlnx_dp_read()
700 ret = s->core_registers[DP_INTERRUPT_SIGNAL_STATE]; in xlnx_dp_read()
701 s->core_registers[DP_INTERRUPT_SIGNAL_STATE] &= ~0x04; in xlnx_dp_read()
727 ret = s->core_registers[DP_INT_MASK]; in xlnx_dp_read()
729 ret = s->core_registers[offset]; in xlnx_dp_read()
752 s->core_registers[offset] = value & 0x000000FF; in xlnx_dp_write()
756 s->core_registers[offset] = value & 0x0000000F; in xlnx_dp_write()
763 s->core_registers[offset] = value & 0x00000003; in xlnx_dp_write()
770 s->core_registers[offset] = value & 0x00000001; in xlnx_dp_write()
773 s->core_registers[offset] = value & 0x00000007; in xlnx_dp_write()
784 s->core_registers[offset] = value & 0x01; in xlnx_dp_write()
802 s->core_registers[offset] = value & 0x00001F0F; in xlnx_dp_write()
803 xlnx_dp_aux_set_command(s, s->core_registers[offset]); in xlnx_dp_write()
809 s->core_registers[offset] = value & 0x0000FFFF; in xlnx_dp_write()
813 s->core_registers[offset] = value & 0x0000FFFF; in xlnx_dp_write()
818 s->core_registers[offset] = value & 0x00007FFF; in xlnx_dp_write()
821 s->core_registers[offset] = value & 0x00000086; in xlnx_dp_write()
825 s->core_registers[offset] = value & 0x00FFFFFF; in xlnx_dp_write()
830 s->core_registers[offset] = value & 0x00000007; in xlnx_dp_write()
833 s->core_registers[offset] = value & 0x0003FFFF; in xlnx_dp_write()
836 s->core_registers[offset] = value & 0x000003FF; in xlnx_dp_write()
839 s->core_registers[offset] = value & 0x00010003; in xlnx_dp_write()
845 s->core_registers[offset] = value & 0x0000000F; in xlnx_dp_write()
861 s->core_registers[offset] = 0x00000000; in xlnx_dp_write()
864 s->core_registers[offset] = value & 0x000FFFFF; in xlnx_dp_write()
879 s->core_registers[offset] = value & 0x00000001; in xlnx_dp_write()
883 s->core_registers[offset] = value & 0x00000007; in xlnx_dp_write()
887 s->core_registers[DP_INT_STATUS] &= ~value; in xlnx_dp_write()
891 s->core_registers[DP_INT_MASK] &= ~value; in xlnx_dp_write()
895 s->core_registers[DP_INT_MASK] |= value; in xlnx_dp_write()
900 s->core_registers[offset] = value; in xlnx_dp_write()
1192 if ((s->core_registers[DP_TRANSMITTER_ENABLE] & 0x01) == 0) { in xlnx_dp_update_display()
1206 s->core_registers[DP_INT_STATUS] |= (1 << 21); in xlnx_dp_update_display()
1213 s->core_registers[DP_INT_STATUS] |= (1 << 21); in xlnx_dp_update_display()
1238 ".core", sizeof(s->core_registers)); in xlnx_dp_init()
1295 s->core_registers[DP_INT_STATUS] |= DP_INT_VBLNK_START; in vblank_hit()
1345 memset(s->core_registers, 0, sizeof(s->core_registers)); in xlnx_dp_reset()
1346 s->core_registers[DP_VERSION_REGISTER] = 0x04010000; in xlnx_dp_reset()
1347 s->core_registers[DP_CORE_ID] = 0x01020000; in xlnx_dp_reset()
1348 s->core_registers[DP_REPLY_STATUS] = 0x00000010; in xlnx_dp_reset()
1349 s->core_registers[DP_MSA_TRANSFER_UNIT_SIZE] = 0x00000040; in xlnx_dp_reset()
1350 s->core_registers[DP_INIT_WAIT] = 0x00000020; in xlnx_dp_reset()
1351 s->core_registers[DP_PHY_RESET] = 0x00010003; in xlnx_dp_reset()
1352 s->core_registers[DP_INT_MASK] = 0xFFFFF03F; in xlnx_dp_reset()
1353 s->core_registers[DP_PHY_STATUS] = 0x00000043; in xlnx_dp_reset()
1354 s->core_registers[DP_INTERRUPT_SIGNAL_STATE] = 0x00000001; in xlnx_dp_reset()