Searched refs:ZYNQ_GEM_NWCFG_MDCCLKDIV (Results 1 – 1 of 1) sorted by relevance
63 #define ZYNQ_GEM_NWCFG_MDCCLKDIV 0x00100000 /* Div pclk by 64, max 160MHz */ macro65 #define ZYNQ_GEM_NWCFG_MDCCLKDIV 0x000c0000 /* Div pclk by 48, max 120MHz */ macro77 ZYNQ_GEM_NWCFG_MDCCLKDIV)