Searched refs:UART5 (Results 1 – 14 of 14) sorted by relevance
| /openbmc/u-boot/include/dt-bindings/clock/ |
| H A D | stm32mp1-clks.h | 34 #define UART5 21 macro
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| /openbmc/linux/include/dt-bindings/clock/ |
| H A D | stm32mp1-clks.h | 34 #define UART5 21 macro
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| /openbmc/openbmc/meta-facebook/meta-yosemitev2/recipes-bsp/u-boot/u-boot-aspeed-sdk/ |
| H A D | 0001-board-aspeed-Add-Mux-for-yosemitev2.patch | 197 ldr r0, =0x1e78909c @ route UART5 to UART Port1, 2016.08.29
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| /openbmc/linux/arch/arm/boot/dts/st/ |
| H A D | stm32mp15xx-dhcor-drc-compact.dtsi | 285 label = "X11-UART5";
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| H A D | stm32f429.dtsi | 337 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART5)>;
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| /openbmc/linux/arch/arm/boot/dts/nxp/imx/ |
| H A D | imx6ull-phytec-tauri.dtsi | 267 /* UART5 * RS232 */
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| /openbmc/linux/arch/arm/boot/dts/nxp/lpc/ |
| H A D | lpc32xx.dtsi | 243 /* UART5 first since it is the default console, ttyS0 */
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| /openbmc/qemu/hw/misc/ |
| H A D | stm32l4x5_rcc.c | 687 APB1ENR1_SET_ENABLE(UART5); in rcc_update_apb1enr()
842 CCIPR_SET_SOURCE(UART5); in rcc_update_ccipr()
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| /openbmc/linux/drivers/clk/nxp/ |
| H A D | clk-lpc32xx.c | 259 LPC32XX_CLK_DEFINE(UART5, "uart5", CLK_GET_RATE_NOCACHE,
1306 LPC32XX_DEFINE_COMPOSITE(UART5, UART5_MUX, UART5_DIV, UART5_GATE),
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| /openbmc/qemu/docs/system/arm/ |
| H A D | aspeed.rst | 138 machines use the ``UART5`` device for a boot console, which is
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| /openbmc/u-boot/arch/arm/dts/ |
| H A D | stm32f429.dtsi | 341 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART5)>;
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| /openbmc/linux/drivers/clk/ |
| H A D | clk-stm32mp1.c | 1898 PCLK(UART5, "uart5", "pclk1", 0, G_UART5),
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| /openbmc/u-boot/arch/arm/mach-aspeed/ast2500/ |
| H A D | platform.S | 799 ldr r0, =0x1e78909c @ route UART5 to UART Port1, 2016.08.29
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| /openbmc/linux/arch/arm/ |
| H A D | Kconfig.debug | 154 0x80014000 | 0xf0014000 | UART5
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