Searched refs:SRR1 (Results 1 – 13 of 13) sorted by relevance
/openbmc/u-boot/arch/powerpc/cpu/mpc8xx/ |
H A D | start.S | 79 mtspr SRR1, r3 /* Make SRR1 match MSR */ 201 EXCEPTION_PROLOG(SRR0, SRR1) 212 EXCEPTION_PROLOG(SRR0, SRR1) 287 mtspr SRR1,r20 315 mtspr SRR1,r0
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/openbmc/u-boot/arch/powerpc/cpu/mpc86xx/ |
H A D | start.S | 86 EXCEPTION_PROLOG(SRR0, SRR1) 97 EXCEPTION_PROLOG(SRR0, SRR1) 350 mtspr SRR1, r3 481 mtspr SRR1, r3 508 mtspr SRR1,r20 536 mtspr SRR1,r0
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/openbmc/linux/arch/powerpc/kernel/ |
H A D | head_32.h | 40 stw r11, SRR1(r10) 97 lwz r9, SRR1(r12)
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H A D | entry_32.S | 490 RESTORE_xSRR(SRR0,SRR1); 497 RESTORE_xSRR(SRR0,SRR1); 505 RESTORE_xSRR(SRR0,SRR1);
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H A D | head_book3s_32.S | 319 stw r11, SRR1(r10) 704 lwz r9, SRR1(r10)
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H A D | exceptions-64e.S | 96 SPECIAL_EXC_STORE(r10,SRR1) 171 SPECIAL_EXC_LOAD(r10,SRR1)
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H A D | asm-offsets.c | 128 OFFSET(SRR1, thread_struct, srr1); in main()
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/openbmc/u-boot/include/ |
H A D | ppc_asm.tmpl | 194 * r21, r22 (SRR0), and r23 (SRR1). 226 EXCEPTION_PROLOG(SRR0, SRR1); \ 265 EXCEPTION_PROLOG(SRR0, SRR1); \
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/openbmc/u-boot/arch/powerpc/cpu/mpc83xx/ |
H A D | start.S | 115 mtspr SRR1, r3 331 EXCEPTION_PROLOG(SRR0, SRR1) 342 EXCEPTION_PROLOG(SRR0, SRR1) 447 mtspr SRR1,r20 475 mtspr SRR1,r0 501 mtspr SRR1, r3 /* Make SRR1 match MSR */
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/openbmc/linux/Documentation/powerpc/ |
H A D | transactional_memory.rst | 269 if (MSR 29:31 ¬ = 0b010 | SRR1 29:31 ¬ = 0b000) then 270 MSR 29:31 <- SRR1 29:31
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H A D | ultravisor.rst | 992 address of the instruction after the ``UV_ESM`` ultracall and ``SRR1`` 1002 MSR values set to the value in ``SRR1``.
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/openbmc/u-boot/arch/powerpc/cpu/mpc85xx/ |
H A D | start.S | 1261 EXCEPTION_PROLOG(SRR0, SRR1) 1272 EXCEPTION_PROLOG(SRR0, SRR1) 1340 mtspr SRR1,r0
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/openbmc/u-boot/arch/powerpc/include/asm/ |
H A D | processor.h | 676 #define SRR1 SPRN_SRR1 /* Save and Restore Register 1 */ macro
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