Searched refs:SRR0 (Results 1 – 13 of 13) sorted by relevance
/openbmc/u-boot/arch/powerpc/cpu/mpc8xx/ |
H A D | start.S | 201 EXCEPTION_PROLOG(SRR0, SRR1) 212 EXCEPTION_PROLOG(SRR0, SRR1) 286 mtspr SRR0,r24 314 mtspr SRR0,r2
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/openbmc/u-boot/arch/powerpc/cpu/mpc86xx/ |
H A D | start.S | 86 EXCEPTION_PROLOG(SRR0, SRR1) 97 EXCEPTION_PROLOG(SRR0, SRR1) 349 mtspr SRR0, r4 480 mtspr SRR0, r4 507 mtspr SRR0,r24 535 mtspr SRR0,r2
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/openbmc/linux/arch/powerpc/kernel/ |
H A D | head_32.h | 38 stw r11, SRR0(r10) 98 lwz r12, SRR0(r12)
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H A D | entry_32.S | 490 RESTORE_xSRR(SRR0,SRR1); 497 RESTORE_xSRR(SRR0,SRR1); 505 RESTORE_xSRR(SRR0,SRR1);
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H A D | head_book3s_32.S | 317 stw r11, SRR0(r10) 703 lwz r4, SRR0(r10)
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H A D | exceptions-64e.S | 94 SPECIAL_EXC_STORE(r10,SRR0) 169 SPECIAL_EXC_LOAD(r10,SRR0)
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H A D | asm-offsets.c | 127 OFFSET(SRR0, thread_struct, srr0); in main()
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/openbmc/u-boot/include/ |
H A D | ppc_asm.tmpl | 194 * r21, r22 (SRR0), and r23 (SRR1). 226 EXCEPTION_PROLOG(SRR0, SRR1); \ 265 EXCEPTION_PROLOG(SRR0, SRR1); \
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/openbmc/u-boot/arch/powerpc/cpu/mpc83xx/ |
H A D | start.S | 114 mtspr SRR0, r4 331 EXCEPTION_PROLOG(SRR0, SRR1) 342 EXCEPTION_PROLOG(SRR0, SRR1) 446 mtspr SRR0,r24 474 mtspr SRR0,r2
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/openbmc/u-boot/arch/powerpc/cpu/mpc85xx/ |
H A D | start.S | 1261 EXCEPTION_PROLOG(SRR0, SRR1) 1272 EXCEPTION_PROLOG(SRR0, SRR1) 1339 mtspr SRR0,r2
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/openbmc/u-boot/arch/powerpc/include/asm/ |
H A D | processor.h | 675 #define SRR0 SPRN_SRR0 /* Save and Restore Register 0 */ macro
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/openbmc/linux/Documentation/powerpc/ |
H A D | transactional_memory.rst | 260 have SRR0 TM = 0 and TS = 00 (ie. TM off and non transaction) and the
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H A D | ultravisor.rst | 991 the UV_ESM ultracall. Further ``SRR0`` is expected to contain the 1001 (**not Ultravisor**), at the address specified in ``SRR0`` with the
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