Searched refs:RVS (Results 1 – 9 of 9) sorted by relevance
/openbmc/qemu/target/riscv/insn_trans/ |
H A D | trans_svinval.c.inc | 29 REQUIRE_EXT(ctx, RVS); 41 REQUIRE_EXT(ctx, RVS); 49 REQUIRE_EXT(ctx, RVS);
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H A D | trans_privileged.c.inc | 80 if (has_ext(ctx, RVS)) {
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/openbmc/qemu/target/riscv/ |
H A D | th_csr.c | 38 if (riscv_has_ext(env, RVS)) { in smode()
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H A D | csr.c | 68 if (env->priv == PRV_U && riscv_has_ext(env, RVS)) { in smstateen_acc_ok() 153 if (riscv_has_ext(env, RVS) && env->priv == PRV_U && in ctr() 291 if (riscv_has_ext(env, RVS)) { in smode() 848 inh_avail_mask |= riscv_has_ext(env, RVS) ? MCYCLECFG_BIT_SINH : 0; in write_mcyclecfg() 874 inh_avail_mask |= riscv_has_ext(env, RVS) ? MCYCLECFGH_BIT_SINH : 0; in write_mcyclecfgh() 878 riscv_has_ext(env, RVS)) ? MCYCLECFGH_BIT_VSINH : 0; in write_mcyclecfgh() 925 inh_avail_mask |= riscv_has_ext(env, RVS) ? MINSTRETCFGH_BIT_SINH : 0; in write_minstretcfgh() 959 inh_avail_mask |= riscv_has_ext(env, RVS) ? MHPMEVENT_BIT_SINH : 0; in write_mhpmevent() 993 inh_avail_mask |= riscv_has_ext(env, RVS) ? MHPMEVENTH_BIT_SINH : 0; in write_mhpmeventh() 997 riscv_has_ext(env, RVS)) ? MHPMEVENTH_BIT_VSINH : 0; in write_mhpmeventh() [all …]
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H A D | cpu.c | 45 RVC, RVS, RVU, RVH, RVJ, RVG, RVB, 0}; 500 riscv_cpu_set_misa_ext(env, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); in rv64_sifive_u_cpu_init() 535 riscv_cpu_set_misa_ext(env, RVG | RVC | RVS | RVU); in rv64_thead_c906_cpu_init() 567 riscv_cpu_set_misa_ext(env, RVG | RVC | RVS | RVU | RVH); in rv64_veyron_v1_cpu_init() 659 riscv_cpu_set_misa_ext(env, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); in rv32_sifive_u_cpu_init() 1406 MISA_EXT_INFO(RVS, "s", "Supervisor-level instructions"), 2245 .misa_ext = RVS,
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H A D | op_helper.c | 359 bool rvs = riscv_has_ext(env, RVS); in helper_wfi()
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H A D | cpu.h | 66 #define RVS RV('S') macro
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/openbmc/qemu/hw/riscv/ |
H A D | boot.c | 58 } else if (riscv_has_ext(env, RVS)) { in riscv_plic_hart_config_string()
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/openbmc/qemu/target/riscv/tcg/ |
H A D | tcg-cpu.c | 439 if (riscv_has_ext(env, RVS) && !riscv_has_ext(env, RVU)) { in riscv_cpu_validate_set_extensions() 451 if (riscv_has_ext(env, RVH) && !riscv_has_ext(env, RVS)) { in riscv_cpu_validate_set_extensions() 1050 MISA_CFG(RVS, true),
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