68     if (env->priv == PRV_U && riscv_has_ext(env, RVS)) {  in smstateen_acc_ok()
153     if (riscv_has_ext(env, RVS) && env->priv == PRV_U &&  in ctr()
291     if (riscv_has_ext(env, RVS)) {  in smode()
848         inh_avail_mask |= riscv_has_ext(env, RVS) ? MCYCLECFG_BIT_SINH : 0;  in write_mcyclecfg()
852                            riscv_has_ext(env, RVS)) ? MCYCLECFG_BIT_VSINH : 0;  in write_mcyclecfg()
874     inh_avail_mask |= riscv_has_ext(env, RVS) ? MCYCLECFGH_BIT_SINH : 0;  in write_mcyclecfgh()
878                        riscv_has_ext(env, RVS)) ? MCYCLECFGH_BIT_VSINH : 0;  in write_mcyclecfgh()
901         inh_avail_mask |= riscv_has_ext(env, RVS) ? MINSTRETCFG_BIT_SINH : 0;  in write_minstretcfg()
905                            riscv_has_ext(env, RVS)) ? MINSTRETCFG_BIT_VSINH : 0;  in write_minstretcfg()
925     inh_avail_mask |= riscv_has_ext(env, RVS) ? MINSTRETCFGH_BIT_SINH : 0;  in write_minstretcfgh()
929                        riscv_has_ext(env, RVS)) ? MINSTRETCFGH_BIT_VSINH : 0;  in write_minstretcfgh()
959         inh_avail_mask |= riscv_has_ext(env, RVS) ? MHPMEVENT_BIT_SINH : 0;  in write_mhpmevent()
963                            riscv_has_ext(env, RVS)) ? MHPMEVENT_BIT_VSINH : 0;  in write_mhpmevent()
993     inh_avail_mask |= riscv_has_ext(env, RVS) ? MHPMEVENTH_BIT_SINH : 0;  in write_mhpmeventh()
997                        riscv_has_ext(env, RVS)) ? MHPMEVENTH_BIT_VSINH : 0;  in write_mhpmeventh()
1548         valid = riscv_has_ext(env, RVS);  in legalize_mpp()