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Searched refs:RVD (Results 1 – 11 of 11) sorted by relevance

/openbmc/qemu/target/riscv/insn_trans/
H A Dtrans_rvzfa.c.inc85 REQUIRE_EXT(ctx, RVD);
218 REQUIRE_EXT(ctx, RVD);
235 REQUIRE_EXT(ctx, RVD);
320 REQUIRE_EXT(ctx, RVD);
337 REQUIRE_EXT(ctx, RVD);
388 REQUIRE_EXT(ctx, RVD);
407 REQUIRE_EXT(ctx, RVD);
422 REQUIRE_EXT(ctx, RVD);
467 REQUIRE_EXT(ctx, RVD);
482 REQUIRE_EXT(ctx, RVD);
H A Dtrans_rvd.c.inc23 REQUIRE_EXT(ctx, RVD); \
36 if (!has_ext(ctx, RVD) || !has_ext(ctx, RVC)) { \
48 REQUIRE_EXT(ctx, RVD);
78 REQUIRE_EXT(ctx, RVD);
548 REQUIRE_EXT(ctx, RVD);
598 REQUIRE_EXT(ctx, RVD);
H A Dtrans_xthead.c.inc381 REQUIRE_EXT(ctx, RVD);
397 REQUIRE_EXT(ctx, RVD);
413 REQUIRE_EXT(ctx, RVD);
429 REQUIRE_EXT(ctx, RVD);
448 REQUIRE_EXT(ctx, RVD);
464 REQUIRE_EXT(ctx, RVD);
H A Dtrans_rvv.c.inc2189 * RVF and RVD can be treated equally.
/openbmc/qemu/target/riscv/
H A Dgdbstub.c117 if (env->misa_ext & RVD) { in riscv_gdb_get_fpu()
332 if (env->misa_ext & RVD) { in riscv_cpu_register_gdb_regs_for_features()
H A Dcpu.c44 const uint32_t misa_bits[] = {RVI, RVE, RVM, RVA, RVF, RVD, RVV,
445 riscv_cpu_set_misa_ext(env, RVI | RVM | RVA | RVF | RVD | RVC | RVU); in riscv_any_cpu_init()
500 riscv_cpu_set_misa_ext(env, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); in rv64_sifive_u_cpu_init()
659 riscv_cpu_set_misa_ext(env, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); in rv32_sifive_u_cpu_init()
1401 MISA_EXT_INFO(RVD, "d", "Double-precision float point"),
2213 .misa_ext = RVI | RVM | RVA | RVF | RVD | RVC | RVU,
2275 .ext = RVD,
2321 .implied_misa_exts = RVD,
2510 .implied_misa_exts = RVD,
H A Dcpu.h63 #define RVD RV('D') macro
H A Dcsr.c1697 val & RVF && val & RVD)) { in write_misa()
/openbmc/qemu/target/riscv/tcg/
H A Dtcg-cpu.c343 uint32_t g_misa_bits[] = {RVI, RVM, RVA, RVF, RVD}; in riscv_cpu_validate_g()
486 if (riscv_has_ext(env, RVD) && !riscv_has_ext(env, RVF)) { in riscv_cpu_validate_set_extensions()
501 if (!riscv_has_ext(env, RVD)) { in riscv_cpu_validate_set_extensions()
567 if (!riscv_has_ext(env, RVD) && cpu->cfg.ext_zcd) { in riscv_cpu_validate_set_extensions()
841 if (riscv_has_ext(env, RVD)) { in cpu_enable_zc_implied_rules()
1045 MISA_CFG(RVD, true),
/openbmc/qemu/target/riscv/kvm/
H A Dkvm-cpu.c181 KVM_MISA_CFG(RVD, KVM_RISCV_ISA_EXT_D),
641 if (riscv_has_ext(env, RVD)) { in kvm_riscv_get_regs_fp()
674 if (riscv_has_ext(env, RVD)) { in kvm_riscv_put_regs_fp()
/openbmc/qemu/linux-user/
H A Dsyscall.c8907 riscv_has_ext(env, RVD) ? in risc_hwprobe_fill_pairs()