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Searched refs:MII_BMSR (Results 1 – 25 of 45) sorted by relevance

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/openbmc/qemu/hw/net/
H A De1000x_common.h81 phy[MII_BMSR] &= ~MII_BMSR_LINK_ST; in e1000x_update_regs_on_link_down()
82 phy[MII_BMSR] &= ~MII_BMSR_AN_COMP; in e1000x_update_regs_on_link_down()
90 phy[MII_BMSR] |= MII_BMSR_LINK_ST; in e1000x_update_regs_on_link_up()
H A Dsunhme.c433 s->miiregs[MII_BMSR] |= MII_BMSR_AN_COMP; in sunhme_mii_write()
437 s->miiregs[MII_BMSR] |= MII_BMSR_LINK_ST; in sunhme_mii_write()
673 s->miiregs[MII_BMSR] &= ~MII_BMSR_LINK_ST; in sunhme_link_status_changed()
676 s->miiregs[MII_BMSR] |= MII_BMSR_LINK_ST; in sunhme_link_status_changed()
906 s->miiregs[MII_BMSR] = MII_BMSR_AUTONEG | MII_BMSR_100TX_FD | in sunhme_reset()
911 s->miiregs[MII_BMSR] |= MII_BMSR_LINK_ST; in sunhme_reset()
H A Dnpcm_gmac.c119 [MII_BMSR] = MII_BMSR_100TX_FD | MII_BMSR_100TX_HD | MII_BMSR_10T_FD |
148 gmac->phy_regs[0][MII_BMSR] |= (MII_BMSR_LINK_ST | MII_BMSR_AN_COMP); in gmac_phy_set_link()
150 gmac->phy_regs[0][MII_BMSR] &= ~(MII_BMSR_LINK_ST | MII_BMSR_AN_COMP); in gmac_phy_set_link()
680 !(gmac->phy_regs[pa][MII_BMSR] & MII_BMSR_AN_COMP)) { in npcm_gmac_mdio_access()
682 gmac->phy_regs[pa][MII_BMSR] |= MII_BMSR_AN_COMP; in npcm_gmac_mdio_access()
850 gmac->phy_regs[0][MII_BMSR]); in npcm_gmac_reset()
H A Dmsf2-emac.c186 s->phy_regs[MII_BMSR] &= ~(MII_BMSR_AN_COMP | in msf2_phy_update_link()
189 s->phy_regs[MII_BMSR] |= (MII_BMSR_AN_COMP | in msf2_phy_update_link()
198 s->phy_regs[MII_BMSR] = 0x7968; in msf2_phy_reset()
228 s->phy_regs[MII_BMSR] |= MII_BMSR_AN_COMP; in write_to_phy()
H A Dopencores_eth.c73 s->regs[MII_BMSR] |= MII_BMSR_LINK_ST; in mii_set_link()
77 s->regs[MII_BMSR] &= ~MII_BMSR_LINK_ST; in mii_set_link()
87 s->regs[MII_BMSR] = MII_BMSR_100TX_FD | MII_BMSR_100TX_HD | in mii_reset()
114 [MII_BMSR] = mii_ro, in mii_write_host()
H A Dlan9118_phy.c45 case MII_BMSR: in lan9118_phy_read()
H A Dallwinner_emac.c67 case MII_BMSR: in RTL8201CP_mdio_read()
116 case MII_BMSR: in RTL8201CP_mdio_write()
/openbmc/u-boot/drivers/net/phy/
H A Dphy.c79 bmsr = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMSR); in genphy_config_advert()
228 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMSR); in genphy_update_link()
263 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMSR); in genphy_update_link()
269 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMSR); in genphy_update_link()
291 int mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMSR); in genphy_parse_link()
392 val = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMSR); in genphy_config()
H A Dsmsc.c20 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMSR); in smsc_parse_status()
H A Dnatsemi.c121 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMSR); in dp83848_parse_status()
/openbmc/u-boot/drivers/net/
H A Ddnet.c228 status = dnet_mdio_read(dnet, MII_BMSR); in dnet_phy_reset()
269 status = dnet_mdio_read(dnet, MII_BMSR); in dnet_phy_init()
275 status = dnet_mdio_read(dnet, MII_BMSR); in dnet_phy_init()
H A Dat91_emac.c201 MII_BMSR, &status); in at91emac_phy_reset()
236 MII_BMSR, &status); in at91emac_phy_init()
245 MII_BMSR, &status); in at91emac_phy_init()
275 at91emac_read(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR, MII_BMSR, &stat1); in at91emac_UpdateLinkSpeed()
H A Dax88180.c340 bmsr_val = ax88180_mdio_read (dev, MII_BMSR); in ax88180_media_config()
347 bmsr_val = ax88180_mdio_read (dev, MII_BMSR); in ax88180_media_config()
362 bmsr_val = ax88180_mdio_read (dev, MII_BMSR); in ax88180_media_config()
H A Dmcfmii.c253 miiphy_read(dev->name, info->phy_addr, MII_BMSR, &status); in __mii_init()
H A Dsmc911x.c99 if (smc911x_eth_phy_read(dev, 1, MII_BMSR, &status) != 0) in smc911x_phy_configure()
H A Dmacb.c455 status = macb_mdio_read(macb, MII_BMSR); in macb_phy_reset()
546 status = macb_mdio_read(macb, MII_BMSR); in macb_phy_init()
552 status = macb_mdio_read(macb, MII_BMSR); in macb_phy_init()
/openbmc/u-boot/arch/arm/mach-davinci/
H A Dlxt972.c101 if (!davinci_eth_phy_read(phy_addr, MII_BMSR, &tmp)) in lxt972_auto_negotiate()
/openbmc/qemu/include/hw/net/
H A Dmii.h26 #define MII_BMSR 1 /* Basic mode status register */ macro
/openbmc/qemu/hw/net/fsl_etsec/
H A Dmiim.c46 case MII_BMSR: in miim_read_cycle()
/openbmc/u-boot/drivers/qe/
H A Duec_phy.c372 uec_phy_read(mii_info, MII_BMSR); in genmii_update_link()
378 status = uec_phy_read(mii_info, MII_BMSR); in genmii_update_link()
394 status = uec_phy_read(mii_info, MII_BMSR); in genmii_update_link()
463 val = uec_phy_read(mii_info, MII_BMSR); in bcm_init()
/openbmc/u-boot/common/
H A Dmiiphyutil.c546 (void)miiphy_read(devname, addr, MII_BMSR, &reg); in miiphy_link()
547 if (miiphy_read(devname, addr, MII_BMSR, &reg)) { in miiphy_link()
/openbmc/u-boot/include/linux/
H A Dmii.h14 #define MII_BMSR 0x01 /* Basic mode status register */ macro
H A Dmdio.h31 #define MDIO_STAT1 MII_BMSR
/openbmc/u-boot/drivers/usb/eth/
H A Dlan75xx.c50 dev->phy_id, MII_BMSR, BMSR_LSTATUS, in lan75xx_phy_gig_workaround()
/openbmc/u-boot/drivers/net/ti/
H A Ddavinci_emac.c358 if (!davinci_eth_phy_read(phy_addr, MII_BMSR, &tmp)) in gen_auto_negotiate()
367 if (!davinci_eth_phy_read(phy_addr, MII_BMSR, &tmp)) in gen_auto_negotiate()

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