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Searched refs:MDIV (Results 1 – 5 of 5) sorted by relevance

/openbmc/u-boot/board/samsung/smdkc100/
H A Dlowlevel_init.S91 ldr r1, =0x81bc0400 @ SDIV 0, PDIV 4, MDIV 444 (1332MHz)
94 ldr r1, =0x80590201 @ SDIV 1, PDIV 2, MDIV 89 (267MHz)
97 ldr r1, =0x80870303 @ SDIV 3, PDIV 3, MDIV 135 (67.5MHz)
/openbmc/u-boot/board/samsung/odroid/
H A Dodroid.c127 clr_pll_con0 = SDIV(7) | PDIV(63) | MDIV(1023) | FSEL(1); in board_clock_init()
128 set = SDIV(0) | PDIV(3) | MDIV(125) | FSEL(1); in board_clock_init()
211 set = SDIV(0) | PDIV(3) | MDIV(100) | FSEL(0) | PLL_ENABLE(1); in board_clock_init()
H A Dsetup.h13 #define MDIV(x) (((x) & 0x3ff) << 16) macro
/openbmc/u-boot/board/samsung/goni/
H A Dlowlevel_init.S257 ldr r1, =0x81bc0400 @ SDIV 0, PDIV 4, MDIV 444 (1333MHz)
260 ldr r1, =0x80590201 @ SDIV 1, PDIV 2, MDIV 89 (267MHz)
263 ldr r1, =0x80870303 @ SDIV 3, PDIV 3, MDIV 135 (67.5MHz)
266 ldr r1, =0x80600603 @ SDIV 3, PDIV 6, MDIV 96
/openbmc/linux/drivers/clk/renesas/
H A Drzg2l-cpg.c46 #define MDIV(val) FIELD_GET(GENMASK(15, 6), val) macro
706 rate = mul_u64_u32_shr(parent_rate, (MDIV(val1) << 16) + KDIV(val1), in rzg2l_cpg_pll_clk_recalc_rate()