Searched refs:J721E_CLK_PARENT_48000 (Results 1 – 1 of 1) sorted by relevance
32 #define J721E_CLK_PARENT_48000 0 macro182 clk_id = J721E_CLK_PARENT_48000; in j721e_configure_refclk()483 clocks->parent[J721E_CLK_PARENT_48000] = parent; in j721e_get_clocks()506 !clocks->parent[J721E_CLK_PARENT_48000]) { in j721e_get_clocks()520 [J721E_CLK_PARENT_48000] = 1179648000, /* PLL4 */529 [J721E_CLK_PARENT_48000] = 1179648000, /* PLL4 */537 [J721E_CLK_PARENT_48000] = 2359296000u, /* PLL4 */576 priv->pll_rates[J721E_CLK_PARENT_48000] = in j721e_calculate_rate_range()577 match_data->pll_rates[J721E_CLK_PARENT_48000]; in j721e_calculate_rate_range()584 !priv->pll_rates[J721E_CLK_PARENT_48000]) { in j721e_calculate_rate_range()[all …]