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Searched refs:ICPU_MEMPHY_CFG_PHY_RST (Results 1 – 6 of 6) sorted by relevance

/openbmc/u-boot/arch/mips/mach-mscc/include/mach/
H A Dddr.h460 ICPU_MEMPHY_CFG_PHY_RST, BASE_CFG + ICPU_MEMPHY_CFG); in hal_vcoreiii_ddr_reset_assert()
649 setbits_le32(BASE_CFG + ICPU_MEMPHY_CFG, ICPU_MEMPHY_CFG_PHY_RST); in hal_vcoreiii_ddr_reset_assert()
/openbmc/u-boot/arch/mips/mach-mscc/include/mach/luton/
H A Dluton_icpu_cfg.h230 #define ICPU_MEMPHY_CFG_PHY_RST BIT(0) macro
/openbmc/u-boot/arch/mips/mach-mscc/include/mach/ocelot/
H A Docelot_icpu_cfg.h242 #define ICPU_MEMPHY_CFG_PHY_RST BIT(0) macro
/openbmc/u-boot/arch/mips/mach-mscc/include/mach/serval/
H A Dserval_icpu_cfg.h281 #define ICPU_MEMPHY_CFG_PHY_RST BIT(0) macro
/openbmc/u-boot/arch/mips/mach-mscc/include/mach/jr2/
H A Djr2_icpu_cfg.h288 #define ICPU_MEMPHY_CFG_PHY_RST BIT(0) macro
/openbmc/u-boot/arch/mips/mach-mscc/include/mach/servalt/
H A Dservalt_icpu_cfg.h286 #define ICPU_MEMPHY_CFG_PHY_RST BIT(0) macro