DRAMTMG2_TCL (reference) in projects: openbmc

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Searched refs:DRAMTMG2_TCL (Results 1 – 4 of 4) sorted by relevance

/openbmc/u-boot/arch/arm/mach-sunxi/dram_timings/
H A D	ddr2_v3s.c	`59 writel(DRAMTMG2_TCWL(tcwl) \| DRAMTMG2_TCL(tcl) \| in mctl_set_timing_params()`
H A D	lpddr3_stock.c	`58 writel(DRAMTMG2_TCWL(tcwl) \| DRAMTMG2_TCL(tcl) \| in mctl_set_timing_params()`
H A D	ddr3_1333.c	`62 writel(DRAMTMG2_TCWL(tcwl) \| DRAMTMG2_TCL(tcl) \| in mctl_set_timing_params()`
/openbmc/u-boot/arch/arm/include/asm/arch-sunxi/
H A D	dram_sunxi_dw.h	`164 #define DRAMTMG2_TCL(x) ((x) << 16) macro`

Last Index Update: Mon Nov 25 03:06:55 CST 2024