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Searched refs:DPLL_MODE_SHIFT (Results 1 – 12 of 12) sorted by relevance

/openbmc/u-boot/arch/arm/include/asm/arch-rockchip/
H A Dcru_rk3036.h92 DPLL_MODE_SHIFT = 4, enumerator
93 DPLL_MODE_MASK = 1 << DPLL_MODE_SHIFT,
H A Dcru_rk322x.h99 DPLL_MODE_SHIFT = 4, enumerator
100 DPLL_MODE_MASK = 1 << DPLL_MODE_SHIFT,
H A Dcru_rk3128.h101 DPLL_MODE_SHIFT = 4, enumerator
102 DPLL_MODE_MASK = 1 << DPLL_MODE_SHIFT,
H A Dcru_rk3288.h197 DPLL_MODE_SHIFT = 4, enumerator
198 DPLL_MODE_MASK = CRU_MODE_MASK << DPLL_MODE_SHIFT,
H A Dcru_rk3188.h163 DPLL_MODE_SHIFT = 4, enumerator
/openbmc/u-boot/drivers/clk/rockchip/
H A Dclk_rk3188.c149 rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK << DPLL_MODE_SHIFT, in rkclk_configure_ddr()
150 DPLL_MODE_SLOW << DPLL_MODE_SHIFT); in rkclk_configure_ddr()
159 rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK << DPLL_MODE_SHIFT, in rkclk_configure_ddr()
160 DPLL_MODE_NORMAL << DPLL_MODE_SHIFT); in rkclk_configure_ddr()
233 0xff, APLL_MODE_SHIFT, DPLL_MODE_SHIFT, CPLL_MODE_SHIFT, in rkclk_pll_get_rate()
H A Dclk_rk322x.c178 0xff, APLL_MODE_SHIFT, DPLL_MODE_SHIFT, 0xff, in rkclk_pll_get_rate()
339 DPLL_MODE_SLOW << DPLL_MODE_SHIFT); in rk322x_ddr_set_clk()
343 DPLL_MODE_NORM << DPLL_MODE_SHIFT); in rk322x_ddr_set_clk()
H A Dclk_rk3288.c206 DPLL_MODE_SLOW << DPLL_MODE_SHIFT); in rkclk_configure_ddr()
216 DPLL_MODE_NORMAL << DPLL_MODE_SHIFT); in rkclk_configure_ddr()
545 0xff, APLL_MODE_SHIFT, DPLL_MODE_SHIFT, CPLL_MODE_SHIFT, in rkclk_pll_get_rate()
H A Dclk_rk3328.c73 DPLL_MODE_SHIFT = 4, enumerator
221 mode_shift = DPLL_MODE_SHIFT; in rkclk_set_pll()
H A Dclk_rk3036.c177 0xff, APLL_MODE_SHIFT, DPLL_MODE_SHIFT, 0xff, in rkclk_pll_get_rate()
H A Dclk_rk3128.c246 0xff, APLL_MODE_SHIFT, DPLL_MODE_SHIFT, CPLL_MODE_SHIFT, in rkclk_pll_get_rate()
/openbmc/u-boot/arch/arm/mach-rockchip/rk3036/
H A Dsdram_rk3036.c333 DPLL_MODE_SLOW << DPLL_MODE_SHIFT); in rkdclk_init()
352 DPLL_MODE_NORM << DPLL_MODE_SHIFT); in rkdclk_init()