Searched refs:DOUT_SCLK_BUS0_PLL (Results 1 – 7 of 7) sorted by relevance
/openbmc/linux/include/dt-bindings/clock/ |
H A D | exynos7-clk.h | 12 #define DOUT_SCLK_BUS0_PLL 2 macro
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/openbmc/u-boot/include/dt-bindings/clock/ |
H A D | exynos7420-clk.h | 15 #define DOUT_SCLK_BUS0_PLL 2 macro
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/openbmc/u-boot/arch/arm/dts/ |
H A D | exynos7420.dtsi | 36 clocks = <&fin_pll>, <&clock_topc DOUT_SCLK_BUS0_PLL>,
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/openbmc/u-boot/drivers/clk/exynos/ |
H A D | clk-exynos7420.c | 72 case DOUT_SCLK_BUS0_PLL: in exynos7420_topc_get_rate()
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/openbmc/linux/Documentation/devicetree/bindings/clock/ |
H A D | samsung,exynos7-clock.yaml | 263 <&clock_topc DOUT_SCLK_BUS0_PLL>,
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/openbmc/linux/arch/arm64/boot/dts/exynos/ |
H A D | exynos7.dtsi | 175 clocks = <&fin_pll>, <&clock_topc DOUT_SCLK_BUS0_PLL>, 189 clocks = <&fin_pll>, <&clock_topc DOUT_SCLK_BUS0_PLL>,
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/openbmc/linux/drivers/clk/samsung/ |
H A D | clk-exynos7.c | 126 DIV(DOUT_SCLK_BUS0_PLL, "dout_sclk_bus0_pll", "mout_topc_bus0_pll_out",
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