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Searched refs:DIDT_SQ_CTRL0__PHASE_OFFSET__SHIFT (Results 1 – 11 of 11) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
H A Dsmu7_powertune.c144 … DIDT_SQ_CTRL0__PHASE_OFFSET_MASK, DIDT_SQ_CTRL0__PHASE_OFFSET__SHIFT, …
286 … DIDT_SQ_CTRL0__PHASE_OFFSET_MASK, DIDT_SQ_CTRL0__PHASE_OFFSET__SHIFT, …
428 … DIDT_SQ_CTRL0__PHASE_OFFSET_MASK, DIDT_SQ_CTRL0__PHASE_OFFSET__SHIFT, …
570 … DIDT_SQ_CTRL0__PHASE_OFFSET_MASK, DIDT_SQ_CTRL0__PHASE_OFFSET__SHIFT, …
751 … DIDT_SQ_CTRL0__PHASE_OFFSET_MASK, DIDT_SQ_CTRL0__PHASE_OFFSET__SHIFT, …
H A Dvega10_powertune.c206 …RL0, DIDT_SQ_CTRL0__PHASE_OFFSET_MASK, DIDT_SQ_CTRL0__PHASE_OFFSET__SHIFT, 0x…
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_7_2_sh_mask.h18272 #define DIDT_SQ_CTRL0__PHASE_OFFSET__SHIFT 0x2 macro
H A Dgfx_8_0_sh_mask.h20490 #define DIDT_SQ_CTRL0__PHASE_OFFSET__SHIFT 0x2 macro
H A Dgfx_8_1_sh_mask.h21092 #define DIDT_SQ_CTRL0__PHASE_OFFSET__SHIFT 0x2 macro
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_sh_mask.h28736 #define DIDT_SQ_CTRL0__PHASE_OFFSET__SHIFT … macro
H A Dgc_9_2_1_sh_mask.h30278 #define DIDT_SQ_CTRL0__PHASE_OFFSET__SHIFT … macro
H A Dgc_9_1_sh_mask.h29956 #define DIDT_SQ_CTRL0__PHASE_OFFSET__SHIFT … macro
H A Dgc_9_4_2_sh_mask.h30 #define DIDT_SQ_CTRL0__PHASE_OFFSET__SHIFT … macro
H A Dgc_10_1_0_sh_mask.h43070 #define DIDT_SQ_CTRL0__PHASE_OFFSET__SHIFT … macro
H A Dgc_10_3_0_sh_mask.h48283 #define DIDT_SQ_CTRL0__PHASE_OFFSET__SHIFT … macro