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Searched refs:DDRC2 (Results 1 – 7 of 7) sorted by relevance

/openbmc/u-boot/arch/arm/dts/
H A Dstm32mp15-ddr.dtsi18 <&rcc DDRC2>,
/openbmc/linux/include/dt-bindings/clock/
H A Dstm32mp13-clks.h180 #define DDRC2 148 macro
H A Dstm32mp1-clks.h238 #define DDRC2 222 macro
/openbmc/u-boot/include/dt-bindings/clock/
H A Dstm32mp1-clks.h238 #define DDRC2 222 macro
/openbmc/u-boot/doc/device-tree-bindings/memory-controllers/
H A Dst,stm32mp1-ddr.txt163 <&rcc_clk DDRC2>,
/openbmc/u-boot/doc/
H A DREADME.b4860qds67 - DDRC2: Five separate DDR3 parts of 16-bit to support 72-bit (ECC) at 1866MT/s, ECC, 2 GB
195 0x0_0000_0000 0x0_7FFF_FFFF DDRC2 2 GB
/openbmc/u-boot/drivers/clk/
H A Dclk_stm32mp1.c499 STM32MP1_CLK(RCC_DDRITFCR, 2, DDRC2, _UNKNOWN_SEL),