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Searched refs:DACR (Results 1 – 19 of 19) sorted by relevance

/openbmc/linux/arch/sh/include/cpu-sh3/cpu/
H A Ddac.h12 #define DACR 0xa40000a4 macro
21 v = __raw_readb(DACR); in sh_dac_enable()
24 __raw_writeb(v,DACR); in sh_dac_enable()
30 v = __raw_readb(DACR); in sh_dac_disable()
33 __raw_writeb(v,DACR); in sh_dac_disable()
/openbmc/linux/arch/arm/include/asm/
H A Duaccess-asm.h71 #define DACR(x...) x macro
73 #define DACR(x...)
87 DACR( mrc p15, 0, \tmp0, c3, c0, 0)
88 DACR( str \tmp0, [sp, #SVC_DACR])
105 DACR( ldr \tmp0, [sp, #SVC_DACR])
106 DACR( mcr p15, 0, \tmp0, c3, c0, 0)
109 #undef DACR
/openbmc/linux/arch/sh/boards/mach-hp6xx/
H A Dsetup.c151 v8 = __raw_readb(DACR); in hp6xx_setup()
153 __raw_writeb(v8,DACR); in hp6xx_setup()
H A Dpm.c117 __raw_writeb(0x1f, DACR); in hp6x0_pm_enter()
/openbmc/u-boot/arch/arm/mach-uniphier/arm32/
H A Dlowlevel_init.S65 mcr p15, 0, r0, c3, c0, 0 @ DACR (Domain Access Control Register)
/openbmc/linux/arch/arm64/boot/dts/allwinner/
H A Dsun50i-a64-sopine-baseboard.dts164 "Right DAC", "DACR",
H A Dsun50i-a64-pine64.dts265 "Right DAC", "DACR",
H A Dsun50i-a64-bananapi-m64.dts335 "Right DAC", "DACR",
H A Dsun50i-a64-teres-i.dts354 "Right DAC", "DACR",
H A Dsun50i-a64-olinuxino.dts350 "Right DAC", "DACR",
H A Dsun50i-a64-orangepi-win.dts334 "Right DAC", "DACR",
H A Dsun50i-a64-pinebook.dts376 "Right DAC", "DACR",
H A Dsun50i-a64-pinetab.dts449 "Right DAC", "DACR",
H A Dsun50i-a64-pinephone.dtsi453 "Right DAC", "DACR",
H A Dsun50i-a64.dtsi159 "Right DAC", "DACR",
/openbmc/linux/arch/arm/boot/dts/allwinner/
H A Dsun8i-a33-olinuxino.dts198 "Right DAC", "DACR",
H A Dsun8i-a33.dtsi193 "Right DAC", "DACR";
/openbmc/linux/arch/arm/mm/
H A DKconfig634 using the DACR (domain access control register) to protect memory
/openbmc/libcper/specification/document/
H A Dcper-json-specification.tex1032 dacr & uint64 & Register DACR. \texttt{UINT32} value null extended to \texttt{UINT64}.\\