1b4b8f2c9SClément Péron// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2cabbaed7SClément Péron// Copyright (c) 2016 ARM Ltd.
3b8bcf0e1SAndre Przywara
4b8bcf0e1SAndre Przywara/dts-v1/;
5b8bcf0e1SAndre Przywara
6b8bcf0e1SAndre Przywara#include "sun50i-a64.dtsi"
7ac904843SVasily Khoruzhick#include "sun50i-a64-cpu-opp.dtsi"
8b8bcf0e1SAndre Przywara
9b8bcf0e1SAndre Przywara#include <dt-bindings/gpio/gpio.h>
10b8bcf0e1SAndre Przywara
11b8bcf0e1SAndre Przywara/ {
12b8bcf0e1SAndre Przywara	model = "BananaPi-M64";
13b8bcf0e1SAndre Przywara	compatible = "sinovoip,bananapi-m64", "allwinner,sun50i-a64";
14b8bcf0e1SAndre Przywara
15b8bcf0e1SAndre Przywara	aliases {
1694f44288SCorentin Labbe		ethernet0 = &emac;
17b8bcf0e1SAndre Przywara		serial0 = &uart0;
18b8bcf0e1SAndre Przywara		serial1 = &uart1;
19b8bcf0e1SAndre Przywara	};
20b8bcf0e1SAndre Przywara
21b8bcf0e1SAndre Przywara	chosen {
22b8bcf0e1SAndre Przywara		stdout-path = "serial0:115200n8";
23b8bcf0e1SAndre Przywara	};
243bc1de8cSIcenowy Zheng
25f4e4453aSJagan Teki	hdmi-connector {
26f4e4453aSJagan Teki		compatible = "hdmi-connector";
27f4e4453aSJagan Teki		type = "a";
28f4e4453aSJagan Teki
29f4e4453aSJagan Teki		port {
30f4e4453aSJagan Teki			hdmi_con_in: endpoint {
31f4e4453aSJagan Teki				remote-endpoint = <&hdmi_out_con>;
32f4e4453aSJagan Teki			};
33f4e4453aSJagan Teki		};
34f4e4453aSJagan Teki	};
35f4e4453aSJagan Teki
3636252668SChen-Yu Tsai	leds {
3736252668SChen-Yu Tsai		compatible = "gpio-leds";
3836252668SChen-Yu Tsai
39e299e6ddSMaxime Ripard		led-0 {
4036252668SChen-Yu Tsai			label = "bananapi-m64:red:pwr";
4136252668SChen-Yu Tsai			gpios = <&pio 3 24 GPIO_ACTIVE_HIGH>; /* PD24 */
4236252668SChen-Yu Tsai			default-state = "on";
4336252668SChen-Yu Tsai		};
4436252668SChen-Yu Tsai
45e299e6ddSMaxime Ripard		led-1 {
4636252668SChen-Yu Tsai			label = "bananapi-m64:green:user";
4736252668SChen-Yu Tsai			gpios = <&pio 4 14 GPIO_ACTIVE_HIGH>; /* PE14 */
4836252668SChen-Yu Tsai		};
4936252668SChen-Yu Tsai
50e299e6ddSMaxime Ripard		led-2 {
5136252668SChen-Yu Tsai			label = "bananapi-m64:blue:user";
5236252668SChen-Yu Tsai			gpios = <&pio 4 15 GPIO_ACTIVE_HIGH>; /* PE15 */
5336252668SChen-Yu Tsai		};
5436252668SChen-Yu Tsai	};
5536252668SChen-Yu Tsai
563bc1de8cSIcenowy Zheng	wifi_pwrseq: wifi_pwrseq {
573bc1de8cSIcenowy Zheng		compatible = "mmc-pwrseq-simple";
583bc1de8cSIcenowy Zheng		reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 */
59*1b9dac68SSamuel Holland		clocks = <&rtc CLK_OSC32K_FANOUT>;
60c266a2b4SChen-Yu Tsai		clock-names = "ext_clock";
613bc1de8cSIcenowy Zheng	};
62b8bcf0e1SAndre Przywara};
63b8bcf0e1SAndre Przywara
64c56689e6SChen-Yu Tsai&codec {
65c56689e6SChen-Yu Tsai	status = "okay";
66c56689e6SChen-Yu Tsai};
67c56689e6SChen-Yu Tsai
68c56689e6SChen-Yu Tsai&codec_analog {
6907de9094SChen-Yu Tsai	cpvdd-supply = <&reg_eldo1>;
70c56689e6SChen-Yu Tsai	status = "okay";
71c56689e6SChen-Yu Tsai};
72c56689e6SChen-Yu Tsai
73ac904843SVasily Khoruzhick&cpu0 {
74ac904843SVasily Khoruzhick	cpu-supply = <&reg_dcdc2>;
75ac904843SVasily Khoruzhick};
76ac904843SVasily Khoruzhick
77ac904843SVasily Khoruzhick&cpu1 {
78ac904843SVasily Khoruzhick	cpu-supply = <&reg_dcdc2>;
79ac904843SVasily Khoruzhick};
80ac904843SVasily Khoruzhick
81ac904843SVasily Khoruzhick&cpu2 {
82ac904843SVasily Khoruzhick	cpu-supply = <&reg_dcdc2>;
83ac904843SVasily Khoruzhick};
84ac904843SVasily Khoruzhick
85ac904843SVasily Khoruzhick&cpu3 {
86ac904843SVasily Khoruzhick	cpu-supply = <&reg_dcdc2>;
87ac904843SVasily Khoruzhick};
88ac904843SVasily Khoruzhick
89c56689e6SChen-Yu Tsai&dai {
90c56689e6SChen-Yu Tsai	status = "okay";
91c56689e6SChen-Yu Tsai};
92c56689e6SChen-Yu Tsai
93f4e4453aSJagan Teki&de {
94f4e4453aSJagan Teki	status = "okay";
95f4e4453aSJagan Teki};
96f4e4453aSJagan Teki
9781866805SJagan Teki&ehci0 {
9881866805SJagan Teki	status = "okay";
9981866805SJagan Teki};
10081866805SJagan Teki
10115ec9598SIcenowy Zheng&ehci1 {
10215ec9598SIcenowy Zheng	status = "okay";
10315ec9598SIcenowy Zheng};
10415ec9598SIcenowy Zheng
10594f44288SCorentin Labbe&emac {
10694f44288SCorentin Labbe	pinctrl-names = "default";
10794f44288SCorentin Labbe	pinctrl-0 = <&rgmii_pins>;
1081a9a8910SChen-Yu Tsai	phy-mode = "rgmii-id";
10994f44288SCorentin Labbe	phy-handle = <&ext_rgmii_phy>;
110bdfe4cebSIcenowy Zheng	phy-supply = <&reg_dc1sw>;
11194f44288SCorentin Labbe	status = "okay";
11294f44288SCorentin Labbe};
11394f44288SCorentin Labbe
114f4e4453aSJagan Teki&hdmi {
115f4e4453aSJagan Teki	hvcc-supply = <&reg_dldo1>;
116f4e4453aSJagan Teki	status = "okay";
117f4e4453aSJagan Teki};
118f4e4453aSJagan Teki
119f4e4453aSJagan Teki&hdmi_out {
120f4e4453aSJagan Teki	hdmi_out_con: endpoint {
121f4e4453aSJagan Teki		remote-endpoint = <&hdmi_con_in>;
122f4e4453aSJagan Teki	};
123f4e4453aSJagan Teki};
124f4e4453aSJagan Teki
125b8bcf0e1SAndre Przywara&i2c1 {
126b8bcf0e1SAndre Przywara	status = "okay";
127b8bcf0e1SAndre Przywara};
128b8bcf0e1SAndre Przywara
129b8bcf0e1SAndre Przywara&i2c1_pins {
130b8bcf0e1SAndre Przywara	bias-pull-up;
131b8bcf0e1SAndre Przywara};
132b8bcf0e1SAndre Przywara
13394f44288SCorentin Labbe&mdio {
13494f44288SCorentin Labbe	ext_rgmii_phy: ethernet-phy@1 {
13594f44288SCorentin Labbe		compatible = "ethernet-phy-ieee802.3-c22";
13694f44288SCorentin Labbe		reg = <1>;
13794f44288SCorentin Labbe	};
13894f44288SCorentin Labbe};
13994f44288SCorentin Labbe
140b8bcf0e1SAndre Przywara&mmc0 {
141b8bcf0e1SAndre Przywara	pinctrl-names = "default";
142b8bcf0e1SAndre Przywara	pinctrl-0 = <&mmc0_pins>;
1430ff75efbSIcenowy Zheng	vmmc-supply = <&reg_dcdc1>;
144b75cb68dSTuomas Tynkkynen	cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>;
145b8bcf0e1SAndre Przywara	disable-wp;
146b8bcf0e1SAndre Przywara	bus-width = <4>;
147b8bcf0e1SAndre Przywara	status = "okay";
148b8bcf0e1SAndre Przywara};
149b8bcf0e1SAndre Przywara
150b8bcf0e1SAndre Przywara&mmc1 {
151b8bcf0e1SAndre Przywara	pinctrl-names = "default";
152b8bcf0e1SAndre Przywara	pinctrl-0 = <&mmc1_pins>;
1530ff75efbSIcenowy Zheng	vmmc-supply = <&reg_dldo2>;
1540ff75efbSIcenowy Zheng	vqmmc-supply = <&reg_dldo4>;
1553bc1de8cSIcenowy Zheng	mmc-pwrseq = <&wifi_pwrseq>;
156b8bcf0e1SAndre Przywara	bus-width = <4>;
157b8bcf0e1SAndre Przywara	non-removable;
158b8bcf0e1SAndre Przywara	status = "okay";
1593bc1de8cSIcenowy Zheng
1603bc1de8cSIcenowy Zheng	brcmf: wifi@1 {
1613bc1de8cSIcenowy Zheng		reg = <1>;
1623bc1de8cSIcenowy Zheng		compatible = "brcm,bcm4329-fmac";
1633bc1de8cSIcenowy Zheng		interrupt-parent = <&r_pio>;
1643bc1de8cSIcenowy Zheng		interrupts = <0 3 IRQ_TYPE_LEVEL_LOW>; /* PL3 */
1653bc1de8cSIcenowy Zheng		interrupt-names = "host-wake";
1663bc1de8cSIcenowy Zheng	};
167b8bcf0e1SAndre Przywara};
168b8bcf0e1SAndre Przywara
169b8bcf0e1SAndre Przywara&mmc2 {
170b8bcf0e1SAndre Przywara	pinctrl-names = "default";
171fa59dd2eSChen-Yu Tsai	pinctrl-0 = <&mmc2_pins>, <&mmc2_ds_pin>;
1720ff75efbSIcenowy Zheng	vmmc-supply = <&reg_dcdc1>;
173b8bcf0e1SAndre Przywara	bus-width = <8>;
174b8bcf0e1SAndre Przywara	non-removable;
175b8bcf0e1SAndre Przywara	cap-mmc-hw-reset;
176b8bcf0e1SAndre Przywara	status = "okay";
177b8bcf0e1SAndre Przywara};
178b8bcf0e1SAndre Przywara
17981866805SJagan Teki&ohci0 {
18081866805SJagan Teki	status = "okay";
18181866805SJagan Teki};
18281866805SJagan Teki
18315ec9598SIcenowy Zheng&ohci1 {
18415ec9598SIcenowy Zheng	status = "okay";
18515ec9598SIcenowy Zheng};
18615ec9598SIcenowy Zheng
1870ff75efbSIcenowy Zheng&r_rsb {
1880ff75efbSIcenowy Zheng	status = "okay";
1890ff75efbSIcenowy Zheng
1900ff75efbSIcenowy Zheng	axp803: pmic@3a3 {
1910ff75efbSIcenowy Zheng		compatible = "x-powers,axp803";
1920ff75efbSIcenowy Zheng		reg = <0x3a3>;
1930ff75efbSIcenowy Zheng		interrupt-parent = <&r_intc>;
19473088dfeSSamuel Holland		interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_LOW>;
19581866805SJagan Teki		x-powers,drive-vbus-en; /* set N_VBUSEN as output pin */
1960ff75efbSIcenowy Zheng	};
1970ff75efbSIcenowy Zheng};
1980ff75efbSIcenowy Zheng
1990ff75efbSIcenowy Zheng#include "axp803.dtsi"
2000ff75efbSIcenowy Zheng
201a24270afSChen-Yu Tsai&ac_power_supply {
202a24270afSChen-Yu Tsai	status = "okay";
203a24270afSChen-Yu Tsai};
204a24270afSChen-Yu Tsai
205a24270afSChen-Yu Tsai&battery_power_supply {
206a24270afSChen-Yu Tsai	status = "okay";
207a24270afSChen-Yu Tsai};
208a24270afSChen-Yu Tsai
20936252668SChen-Yu Tsai&reg_aldo1 {
21036252668SChen-Yu Tsai	/*
21136252668SChen-Yu Tsai	 * This regulator also drives the PE pingroup GPIOs,
21236252668SChen-Yu Tsai	 * which also controls two LEDs.
21336252668SChen-Yu Tsai	 */
21436252668SChen-Yu Tsai	regulator-always-on;
21536252668SChen-Yu Tsai	regulator-min-microvolt = <2800000>;
21636252668SChen-Yu Tsai	regulator-max-microvolt = <2800000>;
21736252668SChen-Yu Tsai	regulator-name = "afvcc-csi";
21836252668SChen-Yu Tsai};
21936252668SChen-Yu Tsai
2200ff75efbSIcenowy Zheng&reg_aldo2 {
2210ff75efbSIcenowy Zheng	regulator-always-on;
2220ff75efbSIcenowy Zheng	regulator-min-microvolt = <1800000>;
2230ff75efbSIcenowy Zheng	regulator-max-microvolt = <3300000>;
2240ff75efbSIcenowy Zheng	regulator-name = "vcc-pl";
2250ff75efbSIcenowy Zheng};
2260ff75efbSIcenowy Zheng
2270ff75efbSIcenowy Zheng&reg_aldo3 {
2280ff75efbSIcenowy Zheng	regulator-always-on;
2290ff75efbSIcenowy Zheng	regulator-min-microvolt = <3000000>;
2300ff75efbSIcenowy Zheng	regulator-max-microvolt = <3000000>;
2310ff75efbSIcenowy Zheng	regulator-name = "vcc-pll-avcc";
2320ff75efbSIcenowy Zheng};
2330ff75efbSIcenowy Zheng
2340ff75efbSIcenowy Zheng&reg_dc1sw {
23536252668SChen-Yu Tsai	/*
23636252668SChen-Yu Tsai	 * This regulator also indirectly drives the PD pingroup GPIOs,
23736252668SChen-Yu Tsai	 * which also controls the power LED.
23836252668SChen-Yu Tsai	 */
23936252668SChen-Yu Tsai	regulator-always-on;
2400ff75efbSIcenowy Zheng	regulator-name = "vcc-phy";
2410ff75efbSIcenowy Zheng};
2420ff75efbSIcenowy Zheng
2430ff75efbSIcenowy Zheng&reg_dcdc1 {
2440ff75efbSIcenowy Zheng	regulator-always-on;
2450ff75efbSIcenowy Zheng	regulator-min-microvolt = <3300000>;
2460ff75efbSIcenowy Zheng	regulator-max-microvolt = <3300000>;
2470ff75efbSIcenowy Zheng	regulator-name = "vcc-3v3";
2480ff75efbSIcenowy Zheng};
2490ff75efbSIcenowy Zheng
2500ff75efbSIcenowy Zheng&reg_dcdc2 {
2510ff75efbSIcenowy Zheng	regulator-always-on;
2520ff75efbSIcenowy Zheng	regulator-min-microvolt = <1040000>;
2530ff75efbSIcenowy Zheng	regulator-max-microvolt = <1300000>;
2540ff75efbSIcenowy Zheng	regulator-name = "vdd-cpux";
2550ff75efbSIcenowy Zheng};
2560ff75efbSIcenowy Zheng
2570ff75efbSIcenowy Zheng/* DCDC3 is polyphased with DCDC2 */
2580ff75efbSIcenowy Zheng
2590ff75efbSIcenowy Zheng&reg_dcdc5 {
2600ff75efbSIcenowy Zheng	regulator-always-on;
2610ff75efbSIcenowy Zheng	regulator-min-microvolt = <1500000>;
2620ff75efbSIcenowy Zheng	regulator-max-microvolt = <1500000>;
2630ff75efbSIcenowy Zheng	regulator-name = "vcc-dram";
2640ff75efbSIcenowy Zheng};
2650ff75efbSIcenowy Zheng
2660ff75efbSIcenowy Zheng&reg_dcdc6 {
2670ff75efbSIcenowy Zheng	regulator-always-on;
2680ff75efbSIcenowy Zheng	regulator-min-microvolt = <1100000>;
2690ff75efbSIcenowy Zheng	regulator-max-microvolt = <1100000>;
2700ff75efbSIcenowy Zheng	regulator-name = "vdd-sys";
2710ff75efbSIcenowy Zheng};
2720ff75efbSIcenowy Zheng
2730ff75efbSIcenowy Zheng&reg_dldo1 {
2740ff75efbSIcenowy Zheng	regulator-min-microvolt = <3300000>;
2750ff75efbSIcenowy Zheng	regulator-max-microvolt = <3300000>;
2760ff75efbSIcenowy Zheng	regulator-name = "vcc-hdmi-dsi";
2770ff75efbSIcenowy Zheng};
2780ff75efbSIcenowy Zheng
2790ff75efbSIcenowy Zheng&reg_dldo2 {
2800ff75efbSIcenowy Zheng	regulator-min-microvolt = <3300000>;
2810ff75efbSIcenowy Zheng	regulator-max-microvolt = <3300000>;
2820ff75efbSIcenowy Zheng	regulator-name = "vcc-wifi";
2830ff75efbSIcenowy Zheng};
2840ff75efbSIcenowy Zheng
2850ff75efbSIcenowy Zheng&reg_dldo4 {
2860ff75efbSIcenowy Zheng	regulator-min-microvolt = <1800000>;
2870ff75efbSIcenowy Zheng	regulator-max-microvolt = <3300000>;
2880ff75efbSIcenowy Zheng	regulator-name = "vcc-wifi-io";
2890ff75efbSIcenowy Zheng};
2900ff75efbSIcenowy Zheng
29181866805SJagan Teki&reg_drivevbus {
29281866805SJagan Teki	regulator-name = "usb0-vbus";
29381866805SJagan Teki	status = "okay";
29481866805SJagan Teki};
29581866805SJagan Teki
2960ff75efbSIcenowy Zheng&reg_eldo1 {
2970ff75efbSIcenowy Zheng	regulator-min-microvolt = <1800000>;
2980ff75efbSIcenowy Zheng	regulator-max-microvolt = <1800000>;
2990ff75efbSIcenowy Zheng	regulator-name = "cpvdd";
3000ff75efbSIcenowy Zheng};
3010ff75efbSIcenowy Zheng
3020ff75efbSIcenowy Zheng&reg_fldo1 {
3030ff75efbSIcenowy Zheng	regulator-min-microvolt = <1200000>;
3040ff75efbSIcenowy Zheng	regulator-max-microvolt = <1200000>;
3050ff75efbSIcenowy Zheng	regulator-name = "vcc-1v2-hsic";
3060ff75efbSIcenowy Zheng};
3070ff75efbSIcenowy Zheng
3080ff75efbSIcenowy Zheng/*
3090ff75efbSIcenowy Zheng * The A64 chip cannot work without this regulator off, although
3100ff75efbSIcenowy Zheng * it seems to be only driving the AR100 core.
3110ff75efbSIcenowy Zheng * Maybe we don't still know well about CPUs domain.
3120ff75efbSIcenowy Zheng */
3130ff75efbSIcenowy Zheng&reg_fldo2 {
3140ff75efbSIcenowy Zheng	regulator-always-on;
3150ff75efbSIcenowy Zheng	regulator-min-microvolt = <1100000>;
3160ff75efbSIcenowy Zheng	regulator-max-microvolt = <1100000>;
3170ff75efbSIcenowy Zheng	regulator-name = "vdd-cpus";
3180ff75efbSIcenowy Zheng};
3190ff75efbSIcenowy Zheng
3200ff75efbSIcenowy Zheng&reg_rtc_ldo {
3210ff75efbSIcenowy Zheng	regulator-name = "vcc-rtc";
3220ff75efbSIcenowy Zheng};
3230ff75efbSIcenowy Zheng
3245cbef9f9SIcenowy Zheng&simplefb_hdmi {
3255cbef9f9SIcenowy Zheng	vcc-hdmi-supply = <&reg_dldo1>;
3265cbef9f9SIcenowy Zheng};
3275cbef9f9SIcenowy Zheng
328c56689e6SChen-Yu Tsai&sound {
329c56689e6SChen-Yu Tsai	status = "okay";
330c56689e6SChen-Yu Tsai	simple-audio-card,widgets = "Headphone", "Headphone Jack",
331c56689e6SChen-Yu Tsai				    "Microphone", "Microphone Jack",
332c56689e6SChen-Yu Tsai				    "Microphone", "Onboard Microphone";
333c56689e6SChen-Yu Tsai	simple-audio-card,routing =
334631e6a35SSamuel Holland			"Left DAC", "DACL",
335631e6a35SSamuel Holland			"Right DAC", "DACR",
336631e6a35SSamuel Holland			"ADCL", "Left ADC",
337631e6a35SSamuel Holland			"ADCR", "Right ADC",
338c56689e6SChen-Yu Tsai			"Headphone Jack", "HP",
339c56689e6SChen-Yu Tsai			"MIC2", "Microphone Jack",
340c56689e6SChen-Yu Tsai			"Onboard Microphone", "MBIAS",
341c56689e6SChen-Yu Tsai			"MIC1", "Onboard Microphone";
342c56689e6SChen-Yu Tsai};
343c56689e6SChen-Yu Tsai
344b8bcf0e1SAndre Przywara&uart0 {
345b8bcf0e1SAndre Przywara	pinctrl-names = "default";
346d91ebb95SChen-Yu Tsai	pinctrl-0 = <&uart0_pb_pins>;
347b8bcf0e1SAndre Przywara	status = "okay";
348b8bcf0e1SAndre Przywara};
349b8bcf0e1SAndre Przywara
350b8bcf0e1SAndre Przywara&uart1 {
351b8bcf0e1SAndre Przywara	pinctrl-names = "default";
352b8bcf0e1SAndre Przywara	pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>;
353c266a2b4SChen-Yu Tsai	uart-has-rtscts;
354b8bcf0e1SAndre Przywara	status = "okay";
355c266a2b4SChen-Yu Tsai
356c266a2b4SChen-Yu Tsai	bluetooth {
357c266a2b4SChen-Yu Tsai		compatible = "brcm,bcm43438-bt";
358*1b9dac68SSamuel Holland		clocks = <&rtc CLK_OSC32K_FANOUT>;
359c266a2b4SChen-Yu Tsai		clock-names = "lpo";
360c266a2b4SChen-Yu Tsai		vbat-supply = <&reg_dldo2>;
361c266a2b4SChen-Yu Tsai		vddio-supply = <&reg_dldo4>;
362c266a2b4SChen-Yu Tsai		device-wakeup-gpios = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6 */
363c266a2b4SChen-Yu Tsai		host-wakeup-gpios = <&r_pio 0 5 GPIO_ACTIVE_HIGH>; /* PL5 */
364c266a2b4SChen-Yu Tsai		shutdown-gpios = <&r_pio 0 4 GPIO_ACTIVE_HIGH>; /* PL4 */
365c266a2b4SChen-Yu Tsai	};
366b8bcf0e1SAndre Przywara};
36715ec9598SIcenowy Zheng
36881866805SJagan Teki&usb_otg {
36981866805SJagan Teki	dr_mode = "otg";
37081866805SJagan Teki	status = "okay";
37181866805SJagan Teki};
37281866805SJagan Teki
373cc072fb6SChen-Yu Tsai&usb_power_supply {
374cc072fb6SChen-Yu Tsai	status = "okay";
375cc072fb6SChen-Yu Tsai};
376cc072fb6SChen-Yu Tsai
37715ec9598SIcenowy Zheng&usbphy {
37881866805SJagan Teki	usb0_id_det-gpios = <&pio 7 9 GPIO_ACTIVE_HIGH>; /* PH9 */
379cc072fb6SChen-Yu Tsai	usb0_vbus_power-supply = <&usb_power_supply>;
38081866805SJagan Teki	usb0_vbus-supply = <&reg_drivevbus>;
38115ec9598SIcenowy Zheng	status = "okay";
38215ec9598SIcenowy Zheng};
383