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Searched refs:CPU_LOG_INT (Results 1 – 9 of 9) sorted by relevance

/openbmc/qemu/target/loongarch/tcg/
H A Dop_helper.c116 qemu_log_mask(CPU_LOG_INT, "%s: TLBRERA " TARGET_FMT_lx "\n", in helper_ertn()
123 qemu_log_mask(CPU_LOG_INT, "%s: ERA " TARGET_FMT_lx "\n", in helper_ertn()
/openbmc/qemu/hw/xtensa/
H A Dmx_pic.c137 qemu_log_mask(CPU_LOG_INT, "%s: CPU %d, irq: %08x, changed_irq: %08x\n", in xtensa_mx_pic_update_cpu()
257 qemu_log_mask(CPU_LOG_INT, in xtensa_mx_pic_ext_reg_write()
305 qemu_log_mask(CPU_LOG_INT, in xtensa_mx_pic_set_irq()
H A Dpic_cpu.c51 qemu_log_mask(CPU_LOG_INT, in check_interrupts()
/openbmc/qemu/hw/intc/
H A Dloongson_liointc.c150 qemu_log_mask(CPU_LOG_INT, "%s: size=%d, addr=%"HWADDR_PRIx", val=%x\n", in liointc_read()
162 qemu_log_mask(CPU_LOG_INT, "%s: size=%d, addr=%"HWADDR_PRIx", val=%x\n", in liointc_write()
H A Dppc-uic.c47 # define LOG_UIC(...) qemu_log_mask(CPU_LOG_INT, ## __VA_ARGS__)
/openbmc/qemu/target/i386/tcg/system/
H A Dsmm_helper.c43 qemu_log_mask(CPU_LOG_INT, "SMM: enter\n"); in do_smm_enter()
44 log_cpu_state_mask(CPU_LOG_INT, CPU(cpu), CPU_DUMP_CCOP); in do_smm_enter()
317 qemu_log_mask(CPU_LOG_INT, "SMM: after RSM\n"); in helper_rsm()
318 log_cpu_state_mask(CPU_LOG_INT, CPU(cpu), CPU_DUMP_CCOP); in helper_rsm()
/openbmc/qemu/target/mips/tcg/
H A Dexception.c144 qemu_log_mask(CPU_LOG_INT, "%s: %d (%s) %d\n", in do_raise_exception_err()
/openbmc/qemu/util/
H A Dlog.c491 { CPU_LOG_INT, "int",
/openbmc/qemu/target/ppc/
H A Dmisc_helper.c93 qemu_log_mask(CPU_LOG_INT, "HV Facility %d is unavailable (%s)\n", in raise_hv_fu_exception()