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/openbmc/qemu/docs/specs/
H A Dacpi_cpu_hotplug.rst1 QEMU<->ACPI BIOS CPU hotplug interface
4 QEMU supports CPU hotplug via ACPI. This document
7 ACPI BIOS GPE.2 handler is dedicated for notifying OS about CPU hot-add
11 Legacy ACPI CPU hotplug interface registers
14 CPU present bitmap for:
18 - One bit per CPU. Bit position reflects corresponding CPU APIC ID. Read-only.
20 to modern CPU hotplug interface, write 0 into it to do switch.
22 QEMU sets corresponding CPU bit on hot-add event and issues SCI
23 with GPE.2 event set. CPU present map is read by ACPI BIOS GPE.2 handler
24 to notify OS about CPU hot-add events. CPU hot-remove isn't supported.
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/openbmc/qemu/docs/system/
H A Dcpu-models-mips.rst.inc1 Supported CPU model configurations on MIPS hosts
4 QEMU supports variety of MIPS CPU models:
6 Supported CPU models for MIPS32 hosts
9 The following CPU models are supported for use on MIPS32 hosts.
10 Administrators / applications are recommended to use the CPU model that
12 mixture of host CPU models between machines, if live migration
13 compatibility is required, use the newest CPU model that is compatible
38 Supported CPU models for MIPS64 hosts
41 The following CPU models are supported for use on MIPS64 hosts.
42 Administrators / applications are recommended to use the CPU model that
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H A Dcpu-models-x86.rst.inc1 Recommendations for KVM CPU model configuration on x86 hosts
5 CPU models on x86 hosts. The goals are to maximise performance, while
6 protecting guest OS against various CPU hardware flaws, and optionally
7 enabling live migration between hosts with heterogeneous CPU models.
10 Two ways to configure CPU models with QEMU / KVM
15 This passes the host CPU model features, model, stepping, exactly to
16 the guest. Note that KVM may filter out some host CPU model features
19 stable CPU is exposed to the guest across hosts. This is the
20 recommended CPU to use, provided live migration is not required.
24 QEMU comes with a number of predefined named CPU models, that
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H A Dgeneric-loader.rst37 The number of the CPU's address space where the data should be
38 loaded. If not specified the address space of the first CPU is used.
49 Setting a CPU's Program Counter
52 The loader device allows the CPU's PC to be set from the command line. This
58 The value to use as the CPU's PC.
61 The number of the CPU whose PC should be set to the specified value.
68 An example of setting CPU 0's PC to 0x8000 is::
89 This specifies the CPU that should be used. This is an
90 optional argument and will cause the CPU's PC to be set to the
94 written to the specified CPU's address space. If not specified, the
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/openbmc/u-boot/drivers/cpu/
H A DKconfig1 config CPU config
2 bool "Enable CPU drivers using Driver Model"
11 bool "Enable MPC83xx CPU driver"
12 depends on CPU
15 Support CPU cores for SoCs of the MPC83xx series.
18 bool "Enable RISC-V CPU driver"
19 depends on CPU && RISCV
21 Support CPU cores for RISC-V architecture.
/openbmc/qemu/docs/system/arm/
H A Dcpu-features.rst1 Arm CPU Features
4 CPU features are optional features that a CPU of supporting type may
5 choose to implement or not. In QEMU, optional CPU features have
6 corresponding boolean CPU proprieties that, when enabled, indicate
8 indicate that it is not implemented. An example of an Arm CPU feature
9 is the Performance Monitoring Unit (PMU). CPU types such as the
16 As not all CPU types support all optional CPU features, then whether or
17 not a CPU property exists depends on the CPU type. For example, CPUs
19 support the AArch32 CPU feature, which may be enabled by disabling the
20 ``aarch64`` CPU property. A CPU type such as the Cortex-A15, which does
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/openbmc/qemu/docs/system/s390x/
H A Dcpu-topology.rst3 CPU topology on s390x
6 Since QEMU 8.2, CPU topology on s390x provides up to 3 levels of
10 The socket container has one or more CPU entries.
11 Each of these CPU entries consists of a bitmap and three CPU attributes:
13 - CPU type
20 This documentation provides general information on S390 CPU topology,
21 how to enable it and explains the new CPU attributes.
22 For information on how to modify the S390 CPU topology and how to
28 To use the CPU topology, you currently need to choose the KVM accelerator.
33 CPU topology facility via the so-called STFLE bit 11 to the VM).
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/openbmc/u-boot/doc/device-tree-bindings/cpu/
H A Dnios2.txt13 - reg: Contains CPU index.
14 - clock-frequency: Contains the clock frequency for CPU, in Hz.
19 - altr,reset-addr: Specifies CPU reset address
20 - altr,exception-addr: Specifies CPU exception address
23 - altr,has-initda: Specifies CPU support initda instruction, should be 1.
24 - altr,has-mmu: Specifies CPU support MMU support.
25 - altr,has-mul: Specifies CPU hardware multipy support.
26 - altr,has-div: Specifies CPU hardware divide support
/openbmc/qemu/docs/about/
H A Dindex.rst9 entire machine (CPU, memory and emulated devices) to run a guest OS.
10 In this mode the CPU may be fully emulated, or it may work with a
12 guest to run directly on the host CPU.
15 where QEMU can launch processes compiled for one CPU on another CPU.
16 In this mode the CPU is always emulated.
/openbmc/u-boot/arch/arm/cpu/armv7/ls102xa/
H A Dpsci.S84 @ r1: input target CPU ID in MPIDR format, original value in r1 may be dropped
85 @ r4: output validated CPU ID if ARM_PSCI_RET_SUCCESS returns, meaningless for
88 @ Get the real CPU number
105 @ Affinity level 0 - CPU: only 0, 1 are valid in LS1021xa.
113 @ r1 = target CPU
119 @ Clear and Get the correct CPU number
135 @ Detect target CPU state
142 @ Reset target CPU
158 @ Do reset on target CPU
164 @ Wait target CPU up
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/openbmc/openbmc-test-automation/systest/
H A Dproc_freq_check.robot25 ${actual_min_freq}= Get CPU Min Frequency
26 ${min_freq_designated_lower_limit}= Get CPU Min Frequency Limit
31 ${err_msg}= Catenate Reported CPU frequency below designated limit.
35 ${actual_max_freq}= Get CPU Max Frequency
36 ${max_freq_designated_limit}= Get CPU Max Frequency Limit
40 ${err_msg}= Catenate Reported CPU frequency above designated limit.
/openbmc/openbmc/meta-openembedded/meta-oe/recipes-support/cpulimit/
H A Dcpulimit_0.2.bb1 SUMMARY = "cpulimit is a tool which limits the CPU usage of a process"
2 …CPU usage of a process (expressed in percentage, not in CPU time). This is useful to control batch…
/openbmc/u-boot/
H A Dconfig.mk25 CPU := $(CONFIG_SYS_CPU:"%"=%)
28 CPU := arm720t
43 CPUDIR=arch/$(ARCH)/cpu$(if $(CPU),/$(CPU),)
/openbmc/qemu/hw/sparc/
H A Dtrace-events4 sun4m_cpu_set_irq_raise(int level) "Raise CPU IRQ %d"
5 sun4m_cpu_set_irq_lower(int level) "Lower CPU IRQ %d"
18 leon3_set_irq(int intno) "Set CPU IRQ %d"
19 leon3_reset_irq(int intno) "Reset CPU IRQ %d"
/openbmc/openbmc/meta-openembedded/meta-oe/recipes-crypto/botan/
H A Dbotan_3.7.1.bb14 CPU ?= "${TARGET_ARCH}"
15 CPU:x86 = "x86_32"
16 CPU:armv7a = "armv7"
17 CPU:armv7ve = "armv7"
23 --cpu="${CPU}" \
/openbmc/qemu/docs/
H A Dmulti-thread-compression.txt27 The process of compression will consume additional CPU cycles, and the
28 extra CPU cycles will increase the migration time. On the other hand,
35 compression, if the source and destination CPU have equal speed,
48 Compression of data will consume extra CPU cycles; so in a system with
49 high overhead of CPU, avoid using this feature. When the network
50 bandwidth is very limited and the CPU resource is adequate, use of
51 multiple thread compression will be very helpful. If both the CPU and
59 CPU: Intel(R) Xeon(R) CPU E5-2680 0 @ 2.70GHz
147 to reduce the CPU consumption when doing (de)compression. If using
/openbmc/openbmc/poky/meta/recipes-devtools/meson/meson/
H A D0001-Make-CPU-family-warnings-fatal.patch4 Subject: [PATCH] Make CPU family warnings fatal
22 - mlog.warning(f'Unknown CPU family {cpu_family}, please report this at https://github.c…
24 + raise EnvironmentException('Unknown CPU family {}, see https://wiki.yoctoproject.org/w…
37 - mlog.warning(f'Unknown CPU family {trial!r}, please report this at '
41 + raise EnvironmentException('Unknown CPU family %s, see https://wiki.yoctoproject.org/wiki/…
/openbmc/qemu/target/s390x/
H A Dinterrupt.c49 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_HARD); in cpu_inject_clock_comparator()
57 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_HARD); in cpu_inject_cpu_timer()
68 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_HARD); in cpu_inject_emergency_signal()
82 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_HARD); in cpu_inject_external_call()
96 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_HARD); in cpu_inject_restart()
109 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_HARD); in cpu_inject_stop()
/openbmc/u-boot/arch/nds32/
H A DMakefile3 head-y := arch/nds32/cpu/$(CPU)/start.o
5 libs-y += arch/nds32/cpu/$(CPU)/
/openbmc/openbmc/meta-openembedded/meta-oe/recipes-devtools/cpuid/
H A Dcpuid_20230614.bb1 SUMMARY = "Linux tool to dump x86 CPUID information about the CPU(s)"
2 DESCRIPTION = "cpuid dumps detailed information about the CPU(s) gathered \
3 from the CPUID instruction, and also determines the exact model of CPU(s). \
/openbmc/u-boot/arch/powerpc/
H A DMakefile3 head-y := arch/powerpc/cpu/$(CPU)/start.o
6 libs-y += arch/powerpc/cpu/$(CPU)/
/openbmc/qemu/target/ppc/
H A Dmmu-hash32.h79 return ldl_phys(CPU(cpu)->as, base + pte_offset); in ppc_hash32_load_hpte0()
87 return ldl_phys(CPU(cpu)->as, base + pte_offset + HASH_PTE_SIZE_32 / 2); in ppc_hash32_load_hpte1()
95 stl_phys(CPU(cpu)->as, base + pte_offset, pte0); in ppc_hash32_store_hpte0()
103 stl_phys(CPU(cpu)->as, base + pte_offset + HASH_PTE_SIZE_32 / 2, pte1); in ppc_hash32_store_hpte1()
/openbmc/openbmc/poky/meta/recipes-support/libjitterentropy/
H A Dlibjitterentropy_3.6.3.bb1 SUMMARY = "Hardware RNG based on CPU timing jitter"
2 DESCRIPTION = "The Jitter RNG provides a noise source using the CPU execution timing jitter. \
5 all environments and on a lot of CPU architectures."
/openbmc/u-boot/board/qualcomm/dragonboard820c/
H A Dreadme.txt295 [ 0.000000] Booting Linux on physical CPU 0x0
297 [ 0.000000] Boot CPU: AArch64 Processor [511f2112]
374 CPU implementer : 0x51
375 CPU architecture: 8
376 CPU variant : 0x1
377 CPU part : 0x211
378 CPU revision : 2
383 CPU implementer : 0x51
384 CPU architecture: 8
385 CPU variant : 0x1
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/openbmc/qemu/target/sparc/
H A Dtrace-events14 sun4m_cpu_interrupt(unsigned int level) "Set CPU IRQ %d"
15 sun4m_cpu_reset_interrupt(unsigned int level) "Reset CPU IRQ %d"
21 sparc64_cpu_check_irqs_reset_irq(int intno) "Reset CPU IRQ (current interrupt 0x%x)"
22 sparc64_cpu_check_irqs_noset_irq(uint32_t tl, uint32_t tt, int intno) "Not setting CPU IRQ: TL=%d c…
23 sparc64_cpu_check_irqs_set_irq(unsigned int i, int old, int new) "Set CPU IRQ %d old=0x%x new=0x%x"

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