Searched refs:AR71XX_DDR_REG_MODE (Results 1 – 4 of 4) sorted by relevance
/openbmc/u-boot/arch/mips/mach-ath79/ar933x/ |
H A D | ddr.c | 143 writel(DDR2_MODE_DLL_VAL, regs + AR71XX_DDR_REG_MODE); in ddr_init() 156 writel(DDR2_MODE_VAL, regs + AR71XX_DDR_REG_MODE); in ddr_init() 195 writel(DDR1_MODE_DLL_VAL, regs + AR71XX_DDR_REG_MODE); in ddr_init() 210 writel(DDR1_MODE_VAL, regs + AR71XX_DDR_REG_MODE); in ddr_init()
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/openbmc/u-boot/arch/mips/mach-ath79/ar934x/ |
H A D | ddr.c | 101 writel(memcfg->mode | 0x100, ddr_regs + AR71XX_DDR_REG_MODE); in ar934x_ddr_init() 126 writel(memcfg->mode, ddr_regs + AR71XX_DDR_REG_MODE); in ar934x_ddr_init()
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/openbmc/u-boot/arch/mips/mach-ath79/qca953x/ |
H A D | ddr.c | 266 writel(DDR1_MODE_DLL_VAL, regs + AR71XX_DDR_REG_MODE); in ddr_init() 284 writel(DDR1_MODE_VAL, regs + AR71XX_DDR_REG_MODE); in ddr_init() 356 writel(DDR2_MODE_DLL_VAL, regs + AR71XX_DDR_REG_MODE); in ddr_init() 374 writel(DDR2_MODE_VAL, regs + AR71XX_DDR_REG_MODE); in ddr_init()
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/openbmc/u-boot/arch/mips/mach-ath79/include/mach/ |
H A D | ar71xx_regs.h | 209 #define AR71XX_DDR_REG_MODE 0x08 macro
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