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Searched refs:APLL_MODE_SHIFT (Results 1 – 11 of 11) sorted by relevance

/openbmc/u-boot/arch/arm/include/asm/arch-rockchip/
H A Dcru_rk3036.h96 APLL_MODE_SHIFT = 0, enumerator
97 APLL_MODE_MASK = 1 << APLL_MODE_SHIFT,
H A Dcru_rk322x.h103 APLL_MODE_SHIFT = 0, enumerator
104 APLL_MODE_MASK = 1 << APLL_MODE_SHIFT,
H A Dcru_rk3128.h105 APLL_MODE_SHIFT = 0, enumerator
106 APLL_MODE_MASK = 1 << APLL_MODE_SHIFT,
H A Dcru_rk3288.h203 APLL_MODE_SHIFT = 0, enumerator
204 APLL_MODE_MASK = CRU_MODE_MASK << APLL_MODE_SHIFT,
H A Dcru_rk3188.h169 APLL_MODE_SHIFT = 0, enumerator
/openbmc/u-boot/drivers/clk/rockchip/
H A Dclk_rk3188.c198 rk_clrsetreg(&cru->cru_mode_con, APLL_MODE_MASK << APLL_MODE_SHIFT, in rkclk_configure_cpu()
199 APLL_MODE_SLOW << APLL_MODE_SHIFT); in rkclk_configure_cpu()
218 rk_clrsetreg(&cru->cru_mode_con, APLL_MODE_MASK << APLL_MODE_SHIFT, in rkclk_configure_cpu()
219 APLL_MODE_NORMAL << APLL_MODE_SHIFT); in rkclk_configure_cpu()
233 0xff, APLL_MODE_SHIFT, DPLL_MODE_SHIFT, CPLL_MODE_SHIFT, in rkclk_pll_get_rate()
H A Dclk_rk3036.c88 APLL_MODE_SLOW << APLL_MODE_SHIFT); in rkclk_init()
165 APLL_MODE_NORM << APLL_MODE_SHIFT); in rkclk_init()
177 0xff, APLL_MODE_SHIFT, DPLL_MODE_SHIFT, 0xff, in rkclk_pll_get_rate()
H A Dclk_rk322x.c89 APLL_MODE_SLOW << APLL_MODE_SHIFT); in rkclk_init()
166 APLL_MODE_NORM << APLL_MODE_SHIFT); in rkclk_init()
178 0xff, APLL_MODE_SHIFT, DPLL_MODE_SHIFT, 0xff, in rkclk_pll_get_rate()
H A Dclk_rk3128.c150 APLL_MODE_SLOW << APLL_MODE_SHIFT); in rkclk_init()
227 APLL_MODE_NORM << APLL_MODE_SHIFT | in rkclk_init()
246 0xff, APLL_MODE_SHIFT, DPLL_MODE_SHIFT, CPLL_MODE_SHIFT, in rkclk_pll_get_rate()
H A Dclk_rk3288.c499 APLL_MODE_SLOW << APLL_MODE_SHIFT); in rk3288_clk_configure_cpu()
533 APLL_MODE_NORMAL << APLL_MODE_SHIFT); in rk3288_clk_configure_cpu()
545 0xff, APLL_MODE_SHIFT, DPLL_MODE_SHIFT, CPLL_MODE_SHIFT, in rkclk_pll_get_rate()
H A Dclk_rk3328.c71 APLL_MODE_SHIFT = 0, enumerator
217 mode_shift = APLL_MODE_SHIFT; in rkclk_set_pll()