| /openbmc/linux/Documentation/hwmon/ |
| H A D | w83627ehf.rst | 10 Addresses scanned: ISA address retrieved from Super I/O registers
18 Addresses scanned: ISA address retrieved from Super I/O registers
26 Addresses scanned: ISA address retrieved from Super I/O registers
34 Addresses scanned: ISA address retrieved from Super I/O registers
42 Addresses scanned: ISA address retrieved from Super I/O registers
50 Addresses scanned: ISA address retrieved from Super I/O registers
58 Addresses scanned: ISA address retrieved from Super I/O registers
66 Addresses scanned: ISA address retrieved from Super I/O registers
207 Future driver development should bear in mind that the following registers have
208 different functions on the 627EHF and the 627DHG. Some registers also have
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| H A D | nct6775.rst | 15 Addresses scanned: ISA address retrieved from Super I/O registers
23 Addresses scanned: ISA address retrieved from Super I/O registers
31 Addresses scanned: ISA address retrieved from Super I/O registers
39 Addresses scanned: ISA address retrieved from Super I/O registers
47 Addresses scanned: ISA address retrieved from Super I/O registers
55 Addresses scanned: ISA address retrieved from Super I/O registers
63 Addresses scanned: ISA address retrieved from Super I/O registers
71 Addresses scanned: ISA address retrieved from Super I/O registers
79 Addresses scanned: ISA address retrieved from Super I/O registers
87 Addresses scanned: ISA address retrieved from Super I/O registers
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| /openbmc/linux/Documentation/devicetree/bindings/interrupt-controller/ |
| H A D | digicolor-ic.txt | 7 registers (IC) area
11 - syscon: A phandle to the syscon node describing UC registers
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| /openbmc/u-boot/arch/arm/dts/ |
| H A D | armada-xp-mv78260.dtsi | 102 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
103 0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */
104 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */
105 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */
106 0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */
107 0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 /* Port 1.0 registers */
108 0x82000000 0 0x84000 MBUS_ID(0xf0, 0x01) 0x84000 0 0x00002000 /* Port 1.1 registers */
109 0x82000000 0 0x88000 MBUS_ID(0xf0, 0x01) 0x88000 0 0x00002000 /* Port 1.2 registers */
110 0x82000000 0 0x8c000 MBUS_ID(0xf0, 0x01) 0x8c000 0 0x00002000 /* Port 1.3 registers */
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| /openbmc/linux/arch/um/os-Linux/ |
| H A D | Makefile | 10 registers.o sigio.o signal.o start_up.o time.o tty.o \
18 main.o mem.o process.o registers.o sigio.o signal.o start_up.o time.o \
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| /openbmc/linux/drivers/thermal/ti-soc-thermal/ |
| H A D | omap3-thermal-data.c | 80 .registers = &omap34xx_mpu_temp_sensor_registers,
148 .registers = &omap36xx_mpu_temp_sensor_registers,
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| H A D | omap5-thermal-data.c | 281 .registers = &omap5430_mpu_temp_sensor_registers,
290 .registers = &omap5430_gpu_temp_sensor_registers,
297 .registers = &omap5430_core_temp_sensor_registers,
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| /openbmc/linux/Documentation/devicetree/bindings/bus/ |
| H A D | mti,mips-cdmm.yaml | 10 Defines a location of the MIPS Common Device Memory Map registers.
22 used to map the MIPS CDMM registers block.
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| /openbmc/linux/Documentation/devicetree/bindings/power/ |
| H A D | mti,mips-cpc.yaml | 10 Defines a location of the MIPS Cluster Power Controller registers.
22 used to map the MIPS CPC registers block.
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| /openbmc/linux/Documentation/devicetree/bindings/watchdog/ |
| H A D | sunplus,sp7021-wdt.yaml | 22 - description: watchdog registers regions
23 - description: miscellaneous control registers regions
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| /openbmc/linux/Documentation/devicetree/bindings/arm/ |
| H A D | arm,versatile-sysreg.yaml | 7 title: Arm Versatile system registers
13 This is a system control registers block, providing multiple low level
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| /openbmc/linux/Documentation/ABI/testing/ |
| H A D | sysfs-driver-tegra-fuse | 8 as decoded from the fuse registers. Bits order/assignment
9 exactly matches the HW registers, including any unused bits.
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| /openbmc/u-boot/doc/ |
| H A D | README.mxc_ocotp | 31 Read operations are implemented as read accesses to the shadow registers,
41 Following this operation, the shadow registers are not reloaded by the
46 registers, as explained by the first paragraph in 46.2.1.3.
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| /openbmc/linux/Documentation/devicetree/bindings/pci/ |
| H A D | intel-gw-pcie.yaml | 31 - description: Controller control and status registers.
32 - description: PCIe configuration registers.
33 - description: Controller application registers.
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| H A D | ti-pci.txt | 23 - reg-names : The first entry must be "ti-conf" for the TI-specific registers
25 registers
45 - reg-names : "ti-conf" for the TI-specific registers
46 "ep_dbics" for the standard configuration registers as
48 "ep_dbics2" for the standard configuration registers as
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| /openbmc/linux/Documentation/devicetree/bindings/dsp/ |
| H A D | mediatek,mt8186-dsp.yaml | 24 - description: Address and size of the DSP config registers
26 - description: Address and size of the DSP secure registers
27 - description: Address and size of the DSP bus registers
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| /openbmc/linux/arch/arm/vfp/ |
| H A D | vfphw.S | 37 VFPFLDMIA r0, r1 @ reload the working registers while
56 VFPFSTMIA r0, r2 @ save the working registers
120 @ d16 - d31 registers
145 @ d16 - d31 registers
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| /openbmc/linux/Documentation/sound/hd-audio/ |
| H A D | intel-multi-link.rst | 94 - hand-over to the DSP for access to multi-link registers, SHIM/IP with LCTL.OFLEN
96 - move of SHIM and Cadence registers to different offsets, with no
185 - hand-over to the DSP for access to multi-link registers, SHIM/IP with LCTL.OFLEN
187 - move of DMIC registers to different offsets, with no change in
255 - hand-over to the DSP for access to multi-link registers, SHIM/IP
257 - move of SHIM and SSP IP registers to different offsets, with no
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| /openbmc/linux/Documentation/arch/ia64/ |
| H A D | fsys.rst | 24 CPU registers.
29 state remains in the CPU registers and some kernel state may
30 be stored in bank 0 of registers r16-r31.
36 - CPU registers may contain a mixture of user-level and kernel-level
128 system call restart. Of course, all "preserved" registers also
131 * Fsyscall-handlers MUST check argument registers for containing a
141 * Fsyscall-handlers MUST NOT write to any stacked registers because
152 user-level, care needs to be taken to clear any scratch registers
167 PSR.ic, switch to bank 0 (bsw.0) and then use the shadow registers as
203 PSR.mfl Unchanged. Note: fsys-mode handlers must not write-registers!
[all …]
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| /openbmc/linux/Documentation/devicetree/bindings/mmc/ |
| H A D | sdhci-common.yaml | 21 and SDHCI_CAPABILITIES_1 registers.
27 SDHCI_CAPABILITIES_1 registers.
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| /openbmc/linux/Documentation/devicetree/bindings/soc/nuvoton/ |
| H A D | nuvoton,gfxi.yaml | 14 The Graphics Core Information (GFXI) are a block of registers in Nuvoton SoCs
15 that analyzes Graphics core behavior and provides information in registers.
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| /openbmc/linux/Documentation/devicetree/bindings/hwmon/ |
| H A D | microchip,lan966x.yaml | 22 - description: PVT registers
23 - description: FAN registers
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| /openbmc/linux/Documentation/hid/ |
| H A D | amd-sfh-hid.rst | 50 registers with the HID core. Transport layer attaches a constant "struct hid_ll_driver" object with
71 1. Command transfer via the C2P mailbox registers.
73 3. Supported sensor info via P2C registers.
75 Commands are sent to MP2 using C2P Mailbox registers. Writing into C2P Message registers generates
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| /openbmc/linux/Documentation/devicetree/bindings/media/ |
| H A D | ti,omap3isp.txt | 11 reg : the two registers sets (physical address and length) for the
12 ISP. The first set contains the core ISP registers up to
14 CSI PHYs and receivers registers.
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| /openbmc/linux/Documentation/devicetree/bindings/phy/ |
| H A D | allwinner,sun50i-a64-usb-phy.yaml | 24 - description: PHY Control registers
25 - description: PHY PMU0 registers
26 - description: PHY PMU1 registers
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