1112fd2ecSBenoît ThébaudeauDriver implementing the fuse API for Freescale's On-Chip OTP Controller (OCOTP) 2112fd2ecSBenoît Thébaudeauon MXC 3112fd2ecSBenoît Thébaudeau 4112fd2ecSBenoît ThébaudeauThis IP can be found on the following SoCs: 5*0454e0c4SAlison Wang - Vybrid VF610, 6112fd2ecSBenoît Thébaudeau - i.MX6. 7112fd2ecSBenoît Thébaudeau 8112fd2ecSBenoît ThébaudeauNote that this IP is different from albeit similar to the IPs of the same name 9112fd2ecSBenoît Thébaudeauthat can be found on the following SoCs: 10112fd2ecSBenoît Thébaudeau - i.MX23, 11112fd2ecSBenoît Thébaudeau - i.MX28, 12112fd2ecSBenoît Thébaudeau - i.MX50. 13112fd2ecSBenoît Thébaudeau 14112fd2ecSBenoît ThébaudeauThe section numbers in this file refer to the i.MX6 Reference Manual. 15112fd2ecSBenoît Thébaudeau 16112fd2ecSBenoît ThébaudeauA fuse word contains 32 fuse bit slots, as explained in 46.2.1. 17112fd2ecSBenoît Thébaudeau 18112fd2ecSBenoît ThébaudeauA bank contains 8 fuse word slots, as explained in 46.2.1 and shown by the 19112fd2ecSBenoît Thébaudeaumemory map in 46.4. 20112fd2ecSBenoît Thébaudeau 21112fd2ecSBenoît ThébaudeauSome fuse bit or word slots may not have the corresponding fuses actually 22112fd2ecSBenoît Thébaudeauimplemented in the fusebox. 23112fd2ecSBenoît Thébaudeau 24112fd2ecSBenoît ThébaudeauSee the README files of the SoCs using this driver in order to know the 25112fd2ecSBenoît Thébaudeauconventions used by U-Boot to store some specific data in the fuses, e.g. MAC 26112fd2ecSBenoît Thébaudeauaddresses. 27112fd2ecSBenoît Thébaudeau 28112fd2ecSBenoît ThébaudeauFuse operations: 29112fd2ecSBenoît Thébaudeau 30112fd2ecSBenoît Thébaudeau Read 31112fd2ecSBenoît Thébaudeau Read operations are implemented as read accesses to the shadow registers, 32112fd2ecSBenoît Thébaudeau using "Bankx Wordy" from the memory map in 46.4. This is explained in 33112fd2ecSBenoît Thébaudeau detail by the first two paragraphs in 46.2.1.2. 34112fd2ecSBenoît Thébaudeau 35112fd2ecSBenoît Thébaudeau Sense 36112fd2ecSBenoît Thébaudeau Sense operations are implemented as the direct fusebox read explained by 37112fd2ecSBenoît Thébaudeau the steps in 46.2.1.2. 38112fd2ecSBenoît Thébaudeau 39112fd2ecSBenoît Thébaudeau Program 40112fd2ecSBenoît Thébaudeau Program operations are implemented as explained by the steps in 46.2.1.3. 41112fd2ecSBenoît Thébaudeau Following this operation, the shadow registers are not reloaded by the 42112fd2ecSBenoît Thébaudeau hardware. 43112fd2ecSBenoît Thébaudeau 44112fd2ecSBenoît Thébaudeau Override 45112fd2ecSBenoît Thébaudeau Override operations are implemented as write accesses to the shadow 46112fd2ecSBenoît Thébaudeau registers, as explained by the first paragraph in 46.2.1.3. 47112fd2ecSBenoît Thébaudeau 48112fd2ecSBenoît ThébaudeauConfiguration: 49112fd2ecSBenoît Thébaudeau 50112fd2ecSBenoît Thébaudeau CONFIG_MXC_OCOTP 51112fd2ecSBenoît Thébaudeau Define this to enable the mxc_ocotp driver. 52