| /openbmc/linux/arch/arc/kernel/ |
| H A D | entry.S | 73 ;################### Non TLB Exception Handling #############################
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| /openbmc/linux/Documentation/arch/openrisc/ |
| H A D | openrisc_port.rst | 103 complete change of TLB miss handling.
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| /openbmc/linux/arch/riscv/ |
| H A D | Kconfig.errata | 52 has been flushed from TLB.
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| /openbmc/linux/Documentation/devicetree/bindings/arm/ |
| H A D | arm,cci-400.yaml | 15 and manage coherency, TLB invalidations and memory barriers.
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| /openbmc/linux/tools/perf/Documentation/ |
| H A D | perf-arm-spe.txt | 80 - Allows correlation between an instruction and events, such as TLB and cache miss. (Data source
152 bit 5 - TLB refill
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| /openbmc/qemu/target/mips/ |
| H A D | cpu-defs.c.inc | 398 /* This is the TLB-based MMU core. */
1048 /* MVPConf1 implemented, TLB shareable, no gating storage support,
1050 and shareable TLB entries, MVP has allocatable TCs, 2 VPEs
1060 /* Usermode has no TLB support */
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| /openbmc/linux/arch/xtensa/ |
| H A D | Kconfig | 158 bool "Core variant has a Full MMU (TLB, Pages, Protection, etc)"
164 ie: it supports a TLB with auto-loading, page protection.
748 MMUv2 compatible kernel memory map: TLB way 5 maps 128MB starting
757 TLB way 6 maps 256MB starting at KSEG_PADDR to 0xb0000000
765 TLB way 6 maps 512MB starting at KSEG_PADDR to 0xa0000000
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| /openbmc/linux/arch/arc/ |
| H A D | Kconfig | 126 -MMU-v3: Variable Page Sz (4k, 8k, 16k), bigger J-TLB (128x4)
127 Shared Address Spaces (for sharing TLB entries in MMU)
231 TLB entries have a per-page Cache Enable Bit.
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| /openbmc/linux/Documentation/firmware-guide/acpi/apei/ |
| H A D | output_format.rst | 55 [cache error][, TLB error][, bus error][, micro-architectural error]
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| /openbmc/linux/Documentation/arch/xtensa/ |
| H A D | mmu.rst | 20 TLB setup proceeds along the following steps.
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| /openbmc/linux/tools/perf/util/ |
| H A D | event.h | 92 PERF_MEM_S(TLB, NA) |\
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| /openbmc/linux/arch/arm/mm/ |
| H A D | proc-xscale.S | 147 mcr p15, 0, r1, c10, c4, 1 @ unlock I-TLB
148 mcr p15, 0, r1, c8, c5, 0 @ invalidate I-TLB
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| /openbmc/linux/arch/ia64/ |
| H A D | Kconfig | 324 bool "MCA recovery from errors other than TLB."
331 about the processors in your systems, such as cache and TLB sizes
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| /openbmc/linux/arch/arm/boot/dts/qcom/ |
| H A D | qcom-sdx55-telit-fn980-tlb.dts | 14 model = "Telit FN980 TLB";
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| /openbmc/qemu/target/arm/ |
| H A D | cpu-features.h | 456 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TLB) == 2; in isar_feature_aa64_tlbirange()
461 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TLB) != 0; in isar_feature_aa64_tlbios()
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| /openbmc/linux/Documentation/arch/x86/x86_64/ |
| H A D | boot-options.rst | 294 Force all IO through the software TLB.
296 Do not initialize the software TLB.
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| /openbmc/u-boot/arch/powerpc/cpu/mpc85xx/ |
| H A D | Kconfig | 1490 int "Number of TLB CAM entries"
1494 Number of TLB CAM entries for Book-E chips. 64 for E500MC,
1510 int "Temporary TLB entry for external debugger"
1526 Select a temporary TLB entry to be used during boot to work
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| /openbmc/u-boot/doc/ |
| H A D | README.ramboot-ppc85xx | 54 - setup DDR TLB
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| H A D | README.arm-relocation | 178 TLB addr = XXXXXXXXXX
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| /openbmc/linux/Documentation/arch/x86/ |
| H A D | iommu.rst | 143 iommu: DMA domain TLB invalidation policy: lazy mode
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| H A D | entry_64.rst | 40 like TLB shootdown.
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| /openbmc/linux/arch/arm/include/asm/ |
| H A D | tlbflush.h | 200 #error Unknown TLB model
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| /openbmc/qemu/target/mips/tcg/ |
| H A D | sysemu_helper.h.inc | 168 /* TLB */
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| /openbmc/linux/Documentation/mm/ |
| H A D | multigen_lru.rst | 37 do not require TLB flushes; clean pages do not require writeback.
62 2. The cost of evicting the former channel is higher due to the TLB
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| /openbmc/linux/Documentation/virt/kvm/ |
| H A D | vcpu-requests.rst | 12 its TLB with a VCPU request. The API consists of the following functions::
112 KVM's common MMU notifier may need to flush all of a guest's TLB
|