Searched refs:TLB (Results 151 – 161 of 161) sorted by relevance
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34 In 1987, Rashid et al. described lazy TLB-flush [RichardRashid87a].321 Describes lazy TLB flush, where one waits for each CPU to pass
2453 ARM64_CPUID_FIELDS(ID_AA64ISAR0_EL1, TLB, RANGE)
1972 * For softmmu, perform the TLB load and compare.2070 /* TLB Hit. */
2243 iommu.strict= [ARM64, X86] Configure TLB invalidation behaviour4010 nptcg= [IA-64] Override max number of concurrent global TLB4717 Disable RADIX GTSE feature and use hcall for TLB6343 <int> -- Number of I/O TLB slabs
1361 /* PURGE TLB */
864 # must provide guarantees on what happens if a clean TLB cache entry is
1751 * For system-mode, perform the TLB load and compare.
1860 TLB and ALB that require a unique MAC address for each slave::
3336 can be mapped from slave TLB->slave LAW->slave SRIO or PCIE outbound
22454 …le-less due to: /opengrok/data/xref/openbmc/linux/Documentation/features/vm/TLB/arch-support.txt.gz22455 …ldren: its children prevent delete: /opengrok/data/xref/openbmc/linux/Documentation/features/vm/TLB
24645 …le-less due to: /opengrok/data/xref/openbmc/linux/Documentation/features/vm/TLB/arch-support.txt.gz24646 …ldren: its children prevent delete: /opengrok/data/xref/openbmc/linux/Documentation/features/vm/TLB