/openbmc/linux/tools/perf/pmu-events/arch/x86/alderlaken/ |
H A D | frontend.json | eafcbb68 Wed Nov 23 21:14:38 CST 2022 Zhengjun Xing <zhengjun.xing@linux.intel.com> perf vendor events intel: Add core event list for Alderlake-N
Alderlake-N only has E-core, it has been moved to non-hybrid code path on the kernel side, so add the cpuid for Alderlake-N separately.
Add core event list for Alderlake-N, it is based on the ADL gracemont v1.16 JSON file.
https://github.com/intel/perfmon/tree/main/ADL/events/
Reviewed-by: Kan Liang <kan.liang@linux.intel.com> Signed-off-by: Xing Zhengjun <zhengjun.xing@linux.intel.com> Cc: Alexander Shishkin <alexander.shishkin@intel.com> Cc: Andi Kleen <ak@linux.intel.com> Cc: Ian Rogers <irogers@google.com> Cc: Ingo Molnar <mingo@redhat.com> Cc: Jiri Olsa <jolsa@kernel.org> Cc: Namhyung Kim <namhyung@kernel.org> Cc: Peter Zijlstra <peterz@infradead.org> Link: https://lore.kernel.org/r/20221124031441.110134-1-zhengjun.xing@linux.intel.com Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
|
H A D | other.json | eafcbb68 Wed Nov 23 21:14:38 CST 2022 Zhengjun Xing <zhengjun.xing@linux.intel.com> perf vendor events intel: Add core event list for Alderlake-N
Alderlake-N only has E-core, it has been moved to non-hybrid code path on the kernel side, so add the cpuid for Alderlake-N separately.
Add core event list for Alderlake-N, it is based on the ADL gracemont v1.16 JSON file.
https://github.com/intel/perfmon/tree/main/ADL/events/
Reviewed-by: Kan Liang <kan.liang@linux.intel.com> Signed-off-by: Xing Zhengjun <zhengjun.xing@linux.intel.com> Cc: Alexander Shishkin <alexander.shishkin@intel.com> Cc: Andi Kleen <ak@linux.intel.com> Cc: Ian Rogers <irogers@google.com> Cc: Ingo Molnar <mingo@redhat.com> Cc: Jiri Olsa <jolsa@kernel.org> Cc: Namhyung Kim <namhyung@kernel.org> Cc: Peter Zijlstra <peterz@infradead.org> Link: https://lore.kernel.org/r/20221124031441.110134-1-zhengjun.xing@linux.intel.com Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
|
H A D | pipeline.json | eafcbb68 Wed Nov 23 21:14:38 CST 2022 Zhengjun Xing <zhengjun.xing@linux.intel.com> perf vendor events intel: Add core event list for Alderlake-N
Alderlake-N only has E-core, it has been moved to non-hybrid code path on the kernel side, so add the cpuid for Alderlake-N separately.
Add core event list for Alderlake-N, it is based on the ADL gracemont v1.16 JSON file.
https://github.com/intel/perfmon/tree/main/ADL/events/
Reviewed-by: Kan Liang <kan.liang@linux.intel.com> Signed-off-by: Xing Zhengjun <zhengjun.xing@linux.intel.com> Cc: Alexander Shishkin <alexander.shishkin@intel.com> Cc: Andi Kleen <ak@linux.intel.com> Cc: Ian Rogers <irogers@google.com> Cc: Ingo Molnar <mingo@redhat.com> Cc: Jiri Olsa <jolsa@kernel.org> Cc: Namhyung Kim <namhyung@kernel.org> Cc: Peter Zijlstra <peterz@infradead.org> Link: https://lore.kernel.org/r/20221124031441.110134-1-zhengjun.xing@linux.intel.com Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
|
H A D | floating-point.json | eafcbb68 Wed Nov 23 21:14:38 CST 2022 Zhengjun Xing <zhengjun.xing@linux.intel.com> perf vendor events intel: Add core event list for Alderlake-N
Alderlake-N only has E-core, it has been moved to non-hybrid code path on the kernel side, so add the cpuid for Alderlake-N separately.
Add core event list for Alderlake-N, it is based on the ADL gracemont v1.16 JSON file.
https://github.com/intel/perfmon/tree/main/ADL/events/
Reviewed-by: Kan Liang <kan.liang@linux.intel.com> Signed-off-by: Xing Zhengjun <zhengjun.xing@linux.intel.com> Cc: Alexander Shishkin <alexander.shishkin@intel.com> Cc: Andi Kleen <ak@linux.intel.com> Cc: Ian Rogers <irogers@google.com> Cc: Ingo Molnar <mingo@redhat.com> Cc: Jiri Olsa <jolsa@kernel.org> Cc: Namhyung Kim <namhyung@kernel.org> Cc: Peter Zijlstra <peterz@infradead.org> Link: https://lore.kernel.org/r/20221124031441.110134-1-zhengjun.xing@linux.intel.com Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
|
H A D | virtual-memory.json | eafcbb68 Wed Nov 23 21:14:38 CST 2022 Zhengjun Xing <zhengjun.xing@linux.intel.com> perf vendor events intel: Add core event list for Alderlake-N
Alderlake-N only has E-core, it has been moved to non-hybrid code path on the kernel side, so add the cpuid for Alderlake-N separately.
Add core event list for Alderlake-N, it is based on the ADL gracemont v1.16 JSON file.
https://github.com/intel/perfmon/tree/main/ADL/events/
Reviewed-by: Kan Liang <kan.liang@linux.intel.com> Signed-off-by: Xing Zhengjun <zhengjun.xing@linux.intel.com> Cc: Alexander Shishkin <alexander.shishkin@intel.com> Cc: Andi Kleen <ak@linux.intel.com> Cc: Ian Rogers <irogers@google.com> Cc: Ingo Molnar <mingo@redhat.com> Cc: Jiri Olsa <jolsa@kernel.org> Cc: Namhyung Kim <namhyung@kernel.org> Cc: Peter Zijlstra <peterz@infradead.org> Link: https://lore.kernel.org/r/20221124031441.110134-1-zhengjun.xing@linux.intel.com Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
|
H A D | cache.json | eafcbb68 Wed Nov 23 21:14:38 CST 2022 Zhengjun Xing <zhengjun.xing@linux.intel.com> perf vendor events intel: Add core event list for Alderlake-N
Alderlake-N only has E-core, it has been moved to non-hybrid code path on the kernel side, so add the cpuid for Alderlake-N separately.
Add core event list for Alderlake-N, it is based on the ADL gracemont v1.16 JSON file.
https://github.com/intel/perfmon/tree/main/ADL/events/
Reviewed-by: Kan Liang <kan.liang@linux.intel.com> Signed-off-by: Xing Zhengjun <zhengjun.xing@linux.intel.com> Cc: Alexander Shishkin <alexander.shishkin@intel.com> Cc: Andi Kleen <ak@linux.intel.com> Cc: Ian Rogers <irogers@google.com> Cc: Ingo Molnar <mingo@redhat.com> Cc: Jiri Olsa <jolsa@kernel.org> Cc: Namhyung Kim <namhyung@kernel.org> Cc: Peter Zijlstra <peterz@infradead.org> Link: https://lore.kernel.org/r/20221124031441.110134-1-zhengjun.xing@linux.intel.com Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
|
H A D | memory.json | eafcbb68 Wed Nov 23 21:14:38 CST 2022 Zhengjun Xing <zhengjun.xing@linux.intel.com> perf vendor events intel: Add core event list for Alderlake-N
Alderlake-N only has E-core, it has been moved to non-hybrid code path on the kernel side, so add the cpuid for Alderlake-N separately.
Add core event list for Alderlake-N, it is based on the ADL gracemont v1.16 JSON file.
https://github.com/intel/perfmon/tree/main/ADL/events/
Reviewed-by: Kan Liang <kan.liang@linux.intel.com> Signed-off-by: Xing Zhengjun <zhengjun.xing@linux.intel.com> Cc: Alexander Shishkin <alexander.shishkin@intel.com> Cc: Andi Kleen <ak@linux.intel.com> Cc: Ian Rogers <irogers@google.com> Cc: Ingo Molnar <mingo@redhat.com> Cc: Jiri Olsa <jolsa@kernel.org> Cc: Namhyung Kim <namhyung@kernel.org> Cc: Peter Zijlstra <peterz@infradead.org> Link: https://lore.kernel.org/r/20221124031441.110134-1-zhengjun.xing@linux.intel.com Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
|
/openbmc/linux/tools/perf/pmu-events/arch/x86/ |
H A D | mapfile.csv | eafcbb68 Wed Nov 23 21:14:38 CST 2022 Zhengjun Xing <zhengjun.xing@linux.intel.com> perf vendor events intel: Add core event list for Alderlake-N
Alderlake-N only has E-core, it has been moved to non-hybrid code path on the kernel side, so add the cpuid for Alderlake-N separately.
Add core event list for Alderlake-N, it is based on the ADL gracemont v1.16 JSON file.
https://github.com/intel/perfmon/tree/main/ADL/events/
Reviewed-by: Kan Liang <kan.liang@linux.intel.com> Signed-off-by: Xing Zhengjun <zhengjun.xing@linux.intel.com> Cc: Alexander Shishkin <alexander.shishkin@intel.com> Cc: Andi Kleen <ak@linux.intel.com> Cc: Ian Rogers <irogers@google.com> Cc: Ingo Molnar <mingo@redhat.com> Cc: Jiri Olsa <jolsa@kernel.org> Cc: Namhyung Kim <namhyung@kernel.org> Cc: Peter Zijlstra <peterz@infradead.org> Link: https://lore.kernel.org/r/20221124031441.110134-1-zhengjun.xing@linux.intel.com Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
|