1eafcbb68SZhengjun Xing[
2eafcbb68SZhengjun Xing    {
3eafcbb68SZhengjun Xing        "BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer is stalled due to any number of reasons, including an L1 miss, WCB full, pagewalk, store address block or store data block, on a load that retires.",
4eafcbb68SZhengjun Xing        "EventCode": "0x05",
5eafcbb68SZhengjun Xing        "EventName": "LD_HEAD.ANY_AT_RET",
6eafcbb68SZhengjun Xing        "SampleAfterValue": "1000003",
7eafcbb68SZhengjun Xing        "UMask": "0xff"
8eafcbb68SZhengjun Xing    },
9eafcbb68SZhengjun Xing    {
10eafcbb68SZhengjun Xing        "BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer is stalled due to a core bound stall including a store address match, a DTLB miss or a page walk that detains the load from retiring.",
11eafcbb68SZhengjun Xing        "EventCode": "0x05",
12eafcbb68SZhengjun Xing        "EventName": "LD_HEAD.L1_BOUND_AT_RET",
13eafcbb68SZhengjun Xing        "SampleAfterValue": "1000003",
14eafcbb68SZhengjun Xing        "UMask": "0xf4"
15eafcbb68SZhengjun Xing    },
16eafcbb68SZhengjun Xing    {
17*b42d103bSIan Rogers        "BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to a DL1 miss.",
18*b42d103bSIan Rogers        "EventCode": "0x05",
19*b42d103bSIan Rogers        "EventName": "LD_HEAD.L1_MISS_AT_RET",
20*b42d103bSIan Rogers        "SampleAfterValue": "1000003",
21*b42d103bSIan Rogers        "UMask": "0x81"
22*b42d103bSIan Rogers    },
23*b42d103bSIan Rogers    {
24eafcbb68SZhengjun Xing        "BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to other block cases.",
25eafcbb68SZhengjun Xing        "EventCode": "0x05",
26eafcbb68SZhengjun Xing        "EventName": "LD_HEAD.OTHER_AT_RET",
27eafcbb68SZhengjun Xing        "PublicDescription": "Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to other block cases such as pipeline conflicts, fences, etc.",
28eafcbb68SZhengjun Xing        "SampleAfterValue": "1000003",
29eafcbb68SZhengjun Xing        "UMask": "0xc0"
30eafcbb68SZhengjun Xing    },
31eafcbb68SZhengjun Xing    {
32eafcbb68SZhengjun Xing        "BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to a pagewalk.",
33eafcbb68SZhengjun Xing        "EventCode": "0x05",
34eafcbb68SZhengjun Xing        "EventName": "LD_HEAD.PGWALK_AT_RET",
35eafcbb68SZhengjun Xing        "SampleAfterValue": "1000003",
36eafcbb68SZhengjun Xing        "UMask": "0xa0"
37eafcbb68SZhengjun Xing    },
38eafcbb68SZhengjun Xing    {
39eafcbb68SZhengjun Xing        "BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to a store address match.",
40eafcbb68SZhengjun Xing        "EventCode": "0x05",
41eafcbb68SZhengjun Xing        "EventName": "LD_HEAD.ST_ADDR_AT_RET",
42eafcbb68SZhengjun Xing        "SampleAfterValue": "1000003",
43eafcbb68SZhengjun Xing        "UMask": "0x84"
44eafcbb68SZhengjun Xing    },
45eafcbb68SZhengjun Xing    {
46eafcbb68SZhengjun Xing        "BriefDescription": "Counts the number of machine clears due to memory ordering caused by a snoop from an external agent. Does not count internally generated machine clears such as those due to memory disambiguation.",
47eafcbb68SZhengjun Xing        "EventCode": "0xc3",
48eafcbb68SZhengjun Xing        "EventName": "MACHINE_CLEARS.MEMORY_ORDERING",
49eafcbb68SZhengjun Xing        "SampleAfterValue": "20003",
50eafcbb68SZhengjun Xing        "UMask": "0x2"
51eafcbb68SZhengjun Xing    },
52eafcbb68SZhengjun Xing    {
53eafcbb68SZhengjun Xing        "BriefDescription": "Counts demand data reads that were not supplied by the L3 cache.",
54eafcbb68SZhengjun Xing        "EventCode": "0xB7",
55eafcbb68SZhengjun Xing        "EventName": "OCR.DEMAND_DATA_RD.L3_MISS",
56eafcbb68SZhengjun Xing        "MSRIndex": "0x1a6,0x1a7",
57eafcbb68SZhengjun Xing        "MSRValue": "0x3F84400001",
58eafcbb68SZhengjun Xing        "SampleAfterValue": "100003",
59eafcbb68SZhengjun Xing        "UMask": "0x1"
60eafcbb68SZhengjun Xing    },
61eafcbb68SZhengjun Xing    {
62eafcbb68SZhengjun Xing        "BriefDescription": "Counts demand data reads that were not supplied by the L3 cache.",
63eafcbb68SZhengjun Xing        "EventCode": "0xB7",
64eafcbb68SZhengjun Xing        "EventName": "OCR.DEMAND_DATA_RD.L3_MISS_LOCAL",
65eafcbb68SZhengjun Xing        "MSRIndex": "0x1a6,0x1a7",
66eafcbb68SZhengjun Xing        "MSRValue": "0x3F84400001",
67eafcbb68SZhengjun Xing        "SampleAfterValue": "100003",
68eafcbb68SZhengjun Xing        "UMask": "0x1"
69eafcbb68SZhengjun Xing    },
70eafcbb68SZhengjun Xing    {
71eafcbb68SZhengjun Xing        "BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the L3 cache.",
72eafcbb68SZhengjun Xing        "EventCode": "0xB7",
73eafcbb68SZhengjun Xing        "EventName": "OCR.DEMAND_RFO.L3_MISS",
74eafcbb68SZhengjun Xing        "MSRIndex": "0x1a6,0x1a7",
75eafcbb68SZhengjun Xing        "MSRValue": "0x3F84400002",
76eafcbb68SZhengjun Xing        "SampleAfterValue": "100003",
77eafcbb68SZhengjun Xing        "UMask": "0x1"
78eafcbb68SZhengjun Xing    },
79eafcbb68SZhengjun Xing    {
80eafcbb68SZhengjun Xing        "BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the L3 cache.",
81eafcbb68SZhengjun Xing        "EventCode": "0xB7",
82eafcbb68SZhengjun Xing        "EventName": "OCR.DEMAND_RFO.L3_MISS_LOCAL",
83eafcbb68SZhengjun Xing        "MSRIndex": "0x1a6,0x1a7",
84eafcbb68SZhengjun Xing        "MSRValue": "0x3F84400002",
85eafcbb68SZhengjun Xing        "SampleAfterValue": "100003",
86eafcbb68SZhengjun Xing        "UMask": "0x1"
87eafcbb68SZhengjun Xing    }
88eafcbb68SZhengjun Xing]
89