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/openbmc/u-boot/arch/arm/mach-aspeed/ast2600/
H A Dplatform.Sc3f3abd8 Thu Jul 25 20:29:03 CDT 2019 Chia-Wei, Wang <chiawei_wang@aspeedtech.com> aspeed: ast2600: set ACTLR.SMP to enable cache use

For CA7-based SoC, we need to set ACTLR.SMP bit to
enable the L1D and unified caches.