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H A Dcm-regbits-34xx.h4e68f5a7 Tue May 08 00:55:21 CDT 2012 Rajendra Nayak <rnayak@ti.com> ARM: OMAP3: Fix CM register bit masks

The register bits for MPU_CLK_SRC and IVA2_CLK_SRC in CM_CLKSEL1_PLL
register are 3 bits wide. Fix the MASK definition accordingly.

Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
4e68f5a7 Tue May 08 00:55:21 CDT 2012 Rajendra Nayak <rnayak@ti.com> ARM: OMAP3: Fix CM register bit masks

The register bits for MPU_CLK_SRC and IVA2_CLK_SRC in CM_CLKSEL1_PLL
register are 3 bits wide. Fix the MASK definition accordingly.

Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>