1d2912cb1SThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */
2c595713dSTony Lindgren #ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_34XX_H
3c595713dSTony Lindgren #define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_34XX_H
4c595713dSTony Lindgren 
5c595713dSTony Lindgren /*
6c595713dSTony Lindgren  * OMAP3430 Clock Management register bits
7c595713dSTony Lindgren  *
8c595713dSTony Lindgren  * Copyright (C) 2007-2008 Texas Instruments, Inc.
9c595713dSTony Lindgren  * Copyright (C) 2007-2008 Nokia Corporation
10c595713dSTony Lindgren  *
11c595713dSTony Lindgren  * Written by Paul Walmsley
12c595713dSTony Lindgren  */
13c595713dSTony Lindgren 
14dfa6d6f8SKevin Hilman #define OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_MASK		(1 << 0)
15ed733619STero Kristo #define OMAP3430_ST_IVA2_SHIFT				0
16c595713dSTony Lindgren #define OMAP3430_CLKTRCTRL_IVA2_MASK			(0x3 << 0)
17801954d3SPaul Walmsley #define OMAP3430_CLKACTIVITY_IVA2_MASK			(1 << 0)
18c595713dSTony Lindgren #define OMAP3430_CLKTRCTRL_MPU_MASK			(0x3 << 0)
19da0747d4SPaul Walmsley #define OMAP3430_ST_AES2_SHIFT				28
20da0747d4SPaul Walmsley #define OMAP3430_ST_SHA12_SHIFT				27
21bf765237SPaul Walmsley #define AM35XX_ST_UART4_SHIFT				23
22da0747d4SPaul Walmsley #define OMAP3430_ST_HDQ_SHIFT				22
23da0747d4SPaul Walmsley #define OMAP3430ES2_ST_SSI_IDLE_SHIFT			8
24da0747d4SPaul Walmsley #define OMAP3430_ST_MAILBOXES_SHIFT			7
258f993a01STero Kristo #define OMAP3430_ST_SAD2D_SHIFT				3
26da0747d4SPaul Walmsley #define OMAP3430_ST_SDMA_SHIFT				2
27c595713dSTony Lindgren #define OMAP3430ES2_ST_USBTLL_SHIFT			2
28c595713dSTony Lindgren #define OMAP3430ES1_CLKTRCTRL_D2D_MASK			(0x3 << 4)
29c595713dSTony Lindgren #define OMAP3430_CLKTRCTRL_L4_MASK			(0x3 << 2)
30c595713dSTony Lindgren #define OMAP3430_CLKTRCTRL_L3_MASK			(0x3 << 0)
31c595713dSTony Lindgren #define OMAP3430ES1_CLKTRCTRL_GFX_MASK			(0x3 << 0)
32801954d3SPaul Walmsley #define OMAP3430ES2_CLKTRCTRL_SGX_MASK			(0x3 << 0)
33da0747d4SPaul Walmsley #define OMAP3430_ST_WDT2_SHIFT				5
34da0747d4SPaul Walmsley #define OMAP3430_ST_32KSYNC_SHIFT			2
35c595713dSTony Lindgren #define OMAP3430_AUTO_PERIPH_DPLL_MASK			(0x7 << 3)
36da0747d4SPaul Walmsley #define OMAP3430ES2_ST_DSS_IDLE_SHIFT			1
37c595713dSTony Lindgren #define OMAP3430_CLKTRCTRL_DSS_MASK			(0x3 << 0)
38c595713dSTony Lindgren #define OMAP3430_CLKTRCTRL_CAM_MASK			(0x3 << 0)
39da0747d4SPaul Walmsley #define OMAP3430_ST_MCBSP4_SHIFT			2
40da0747d4SPaul Walmsley #define OMAP3430_ST_MCBSP3_SHIFT			1
41da0747d4SPaul Walmsley #define OMAP3430_ST_MCBSP2_SHIFT			0
42c595713dSTony Lindgren #define OMAP3430_CLKTRCTRL_PER_MASK			(0x3 << 0)
43c595713dSTony Lindgren #define OMAP3430_CLKTRCTRL_EMU_MASK			(0x3 << 0)
44c595713dSTony Lindgren #define OMAP3430_CLKTRCTRL_NEON_MASK			(0x3 << 0)
45c595713dSTony Lindgren #define OMAP3430ES2_EN_USBHOST2_SHIFT			1
46da0747d4SPaul Walmsley #define OMAP3430ES2_ST_USBHOST_IDLE_SHIFT		1
47c595713dSTony Lindgren #define OMAP3430ES2_CLKTRCTRL_USBHOST_MASK		(3 << 0)
48bd2122caSPaul Walmsley #define OMAP34XX_CLKSTCTRL_DISABLE_AUTO		0x0
49bd2122caSPaul Walmsley #define OMAP34XX_CLKSTCTRL_FORCE_SLEEP		0x1
50bd2122caSPaul Walmsley #define OMAP34XX_CLKSTCTRL_FORCE_WAKEUP		0x2
51bd2122caSPaul Walmsley #define OMAP34XX_CLKSTCTRL_ENABLE_AUTO		0x3
52c595713dSTony Lindgren #endif
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