| /openbmc/qemu/hw/arm/ |
| H A D | npcm7xx.c | 2 * Nuvoton NPCM7xx SoC family.
20 #include "hw/arm/npcm7xx.h"
410 NPCM7xxState *s = NPCM7XX(obj); in npcm7xx_init()
478 NPCM7xxState *s = NPCM7XX(dev); in npcm7xx_realize()
483 error_setg(errp, "%s: NPCM7xx cannot address more than %" PRIu64 in npcm7xx_realize()
778 create_unimplemented_device("npcm7xx.shm", 0xc0001000, 4 * KiB); in npcm7xx_realize()
779 create_unimplemented_device("npcm7xx.vdmx", 0xe0800000, 4 * KiB); in npcm7xx_realize()
780 create_unimplemented_device("npcm7xx.pcierc", 0xe1000000, 64 * KiB); in npcm7xx_realize()
781 create_unimplemented_device("npcm7xx.kcs", 0xf0007000, 4 * KiB); in npcm7xx_realize()
782 create_unimplemented_device("npcm7xx.gfxi", 0xf000e000, 4 * KiB); in npcm7xx_realize()
[all …]
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| /openbmc/openbmc/meta-phosphor/classes/ |
| H A D | image_types_phosphor_nuvoton.bbclass | 7 IGPS_DIR = "${STAGING_DIR_NATIVE}/${datadir}/npcm7xx-igps"
9 # Prepare the Bootblock and U-Boot images using npcm7xx-bingo
26 npcm7xx-bootblock:do_deploy \
27 npcm7xx-bingo-native:do_populate_sysroot \
28 npcm7xx-igps-native:do_populate_sysroot \
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| /openbmc/openbmc-test-automation/oem/nuvoton/ |
| H A D | test_jtag_master.robot | 72 ${cpld_firmware1}= Set Variable ${olympus_json["npcm7xx"]["cpld"]["fw1"]}
73 ${cpld_firmware2}= Set Variable ${olympus_json["npcm7xx"]["cpld"]["fw2"]}
74 ${firmware_version1}= Set Variable ${olympus_json["npcm7xx"]["cpld"]["fw1ver"]}
75 ${firmware_version2}= Set Variable ${olympus_json["npcm7xx"]["cpld"]["fw2ver"]}
76 ${readusercode_svf}= Set Variable ${olympus_json["npcm7xx"]["cpld"]["readusercode"]}
77 ${readid_svf}= Set Variable ${olympus_json["npcm7xx"]["cpld"]["readid"]}
78 ${jtag_dev}= Set Variable ${olympus_json["npcm7xx"]["jtag_dev"]}
79 ${power_cycle_cmd}= Set Variable ${olympus_json["npcm7xx"]["power_cycle_cmd"]}
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| /openbmc/openbmc/meta-nuvoton/ |
| H A D | README.md | 1 Nuvoton NPCM7XX
4 This is the Nuvoton NPCM7XX Board Support Package (BSP) layer.
5 The NPCM7XX is an ARM based SoC with external DDR RAM and
7 More information about the NPCM7XX can be found
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| /openbmc/openbmc/meta-nuvoton/conf/machine/include/ |
| H A D | npcm7xx.inc | 2 #@NAME: Nuvoton NPCM7XX
3 #@DESCRIPTION: Common machine configuration for Nuvoton NPCM7XX Chip
29 SOC_FAMILY = "npcm7xx"
31 MACHINEOVERRIDES .= ":npcm7xx"
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| /openbmc/linux/Documentation/devicetree/bindings/gpio/ |
| H A D | nuvoton,sgpio.yaml | 13 This SGPIO controller is for NUVOTON NPCM7xx and NPCM8xx SoC and detailed
14 information is in the NPCM7XX/8XX SERIAL I/O EXPANSION INTERFACE section.
15 Nuvoton NPCM7xx SGPIO module is combines a serial to parallel IC (HC595)
19 NPCM7xx/NPCM8xx have two sgpio modules. Each module can support up
76 #include <dt-bindings/clock/nuvoton,npcm7xx-clock.h>
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| /openbmc/qemu/include/hw/arm/ |
| H A D | npcm7xx.h | 2 * Nuvoton NPCM7xx SoC family.
67 #define TYPE_NPCM7XX_MACHINE MACHINE_TYPE_NAME("npcm7xx")
113 #define TYPE_NPCM7XX "npcm7xx"
114 OBJECT_DECLARE_TYPE(NPCM7xxState, NPCM7xxClass, NPCM7XX)
133 * This will set up the ARM boot info structure for the specific NPCM7xx
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| /openbmc/linux/drivers/usb/host/ |
| H A D | ehci-npcm7xx.c | 3 * Nuvoton NPCM7xx driver for EHCI HCD
25 #define DRIVER_DESC "EHCI npcm7xx driver"
56 dev_dbg(&pdev->dev, "initializing npcm7xx ehci USB Controller\n"); in npcm7xx_ehci_hcd_drv_probe()
128 .name = "npcm7xx-ehci",
152 MODULE_ALIAS("platform:npcm7xx-ehci");
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| /openbmc/linux/arch/arm/mach-npcm/ |
| H A D | Kconfig | 21 bool "Support for NPCM7xx BMC (Poleg)"
38 General support for NPCM7xx BMC (Poleg).
40 Nuvoton NPCM7xx BMC based on the Cortex A9.
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| /openbmc/qemu/include/hw/nvram/ |
| H A D | npcm7xx_otp.h | 2 * Nuvoton NPCM7xx OTP (Fuse Array) Interface
58 #define TYPE_NPCM7XX_OTP "npcm7xx-otp"
61 #define TYPE_NPCM7XX_KEY_STORAGE "npcm7xx-key-storage"
62 #define TYPE_NPCM7XX_FUSE_ARRAY "npcm7xx-fuse-array"
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| /openbmc/openbmc/meta-nuvoton/recipes-bsp/images/ |
| H A D | npcm7xx-bootblock_10.10.19.bb | 1 SUMMARY = "Primary bootloader for NPCM7XX (Poleg) devices"
2 DESCRIPTION = "Primary bootloader for NPCM7XX (Poleg) devices"
3 HOMEPAGE = "https://github.com/Nuvoton-Israel/npcm7xx-bootblock"
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| /openbmc/linux/Documentation/devicetree/bindings/timer/ |
| H A D | nuvoton,npcm7xx-timer.yaml | 4 $id: http://devicetree.org/schemas/timer/nuvoton,npcm7xx-timer.yaml#
7 title: Nuvoton NPCM7xx timer
48 #include <dt-bindings/clock/nuvoton,npcm7xx-clock.h>
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| /openbmc/linux/Documentation/devicetree/bindings/iio/adc/ |
| H A D | nuvoton,npcm750-adc.yaml | 13 The NPCM7XX ADC is a 10-bit converter and NPCM8XX ADC is a 12-bit converter,
54 #include <dt-bindings/clock/nuvoton,npcm7xx-clock.h>
55 #include <dt-bindings/reset/nuvoton,npcm7xx-reset.h>
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| /openbmc/linux/Documentation/devicetree/bindings/reset/ |
| H A D | nuvoton,npcm750-reset.yaml | 15 - nuvoton,npcm750-reset # Poleg NPCM7XX SoC
64 #include <dt-bindings/reset/nuvoton,npcm7xx-reset.h>
73 // Specifying reset lines connected to IP NPCM7XX modules
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| /openbmc/linux/Documentation/devicetree/bindings/spi/ |
| H A D | nuvoton,npcm-fiu.txt | 5 The NPCM7XX supports three FIU modules,
14 - compatible : "nuvoton,npcm750-fiu" for Poleg NPCM7XX BMC
33 In the NPCM7XX BMC:
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| /openbmc/linux/Documentation/devicetree/bindings/i2c/ |
| H A D | nuvoton,npcm7xx-i2c.yaml | 4 $id: http://devicetree.org/schemas/i2c/nuvoton,npcm7xx-i2c.yaml#
7 title: nuvoton NPCM7XX I2C Controller
66 #include <dt-bindings/clock/nuvoton,npcm7xx-clock.h>
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| /openbmc/qemu/include/hw/adc/ |
| H A D | npcm7xx_adc.h | 2 * Nuvoton NPCM7xx ADC Module
27 * hw/arm/npcm7xx.c is also changed.
65 #define TYPE_NPCM7XX_ADC "npcm7xx-adc"
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| /openbmc/qemu/include/hw/misc/ |
| H A D | npcm7xx_gcr.h | 2 * Nuvoton NPCM7xx System Global Control Registers.
23 * NPCM7XX PWRON STRAP bit fields
70 #define TYPE_NPCM7XX_GCR "npcm7xx-gcr"
|
| H A D | npcm7xx_rng.h | 2 * Nuvoton NPCM7xx Random Number Generator.
31 #define TYPE_NPCM7XX_RNG "npcm7xx-rng"
|
| /openbmc/openbmc/meta-phosphor/dynamic-layers/nuvoton-layer/recipes-phosphor/host/ |
| H A D | phosphor-host-postd_%.bbappend | 1 SNOOP_DEVICE:npcm7xx = "npcm7xx-lpc-bpc0"
|
| /openbmc/openbmc/meta-google/recipes-google/bare-metal-espi/bare-metal-espi/ |
| H A D | disable-espi.service | 9 ExecStart=/usr/libexec/npcm7xx-espi-control -d
10 ExecStop=/usr/libexec/npcm7xx-espi-control
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| /openbmc/linux/Documentation/devicetree/bindings/clock/ |
| H A D | nuvoton,npcm750-clk.txt | 1 * Nuvoton NPCM7XX Clock Controller
3 Nuvoton Poleg BMC NPCM7XX contains an integrated clock controller, which
17 dt-bindings/clock/nuvoton,npcm7xx-clock.h
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| /openbmc/qemu/include/hw/timer/ |
| H A D | npcm7xx_timer.h | 2 * Nuvoton NPCM7xx Timer Controller
35 #define NPCM7XX_WATCHDOG_RESET_GPIO_OUT "npcm7xx-clk-watchdog-reset-gpio-out"
109 #define TYPE_NPCM7XX_TIMER "npcm7xx-timer"
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| /openbmc/linux/drivers/clocksource/ |
| H A D | timer-npcm7xx.c | 138 .name = "npcm7xx-timer0",
184 "npcm7xx-timer1", timer_of_rate(&npcm7xx_to), in npcm7xx_clocksource_init()
215 pr_info("Enabling NPCM7xx clocksource timer base: %px, IRQ: %d ", in npcm7xx_timer_init()
222 TIMER_OF_DECLARE(npcm7xx, "nuvoton,npcm750-timer", npcm7xx_timer_init);
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| /openbmc/openbmc/meta-nuvoton/recipes-kernel/linux/ |
| H A D | linux-nuvoton.inc | 1 DESCRIPTION = "Linux kernel for Nuvoton NPCM7xx"
11 SRC_URI:append:npcm7xx = " file://defconfig"
|