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/openbmc/linux/Documentation/fb/
H A Dviafb.modes14 # Scan Frequency 31.469 kHz 59.94 Hz
29 # D: 25.175 MHz, H: 31.469 kHz, V: 59.94 Hz
32 # D: 24.823 MHz, H: 39.780 kHz, V: 60.00 Hz
39 # Scan Frequency 37.500 kHz 75.00 Hz
53 # D: 31.50 MHz, H: 37.500 kHz, V: 75.00 Hz
60 # Scan Frequency 43.269 kHz 85.00 Hz
74 # D: 36.000 MHz, H: 43.269 kHz, V: 85.00 Hz
81 # Scan Frequency 50.900 kHz 100.00 Hz
95 # D: 43.163 MHz, H: 50.900 kHz, V: 100.00 Hz
102 # Scan Frequency 61.800 kHz 120.00 Hz
[all …]
/openbmc/linux/sound/ppc/
H A Dawacs.h112 #define SAMPLERATE_48000 (0x0 << 3) /* 48 or 44.1 kHz */
113 #define SAMPLERATE_32000 (0x1 << 3) /* 32 or 29.4 kHz */
114 #define SAMPLERATE_24000 (0x2 << 3) /* 24 or 22.05 kHz */
115 #define SAMPLERATE_19200 (0x3 << 3) /* 19.2 or 17.64 kHz */
116 #define SAMPLERATE_16000 (0x4 << 3) /* 16 or 14.7 kHz */
117 #define SAMPLERATE_12000 (0x5 << 3) /* 12 or 11.025 kHz */
118 #define SAMPLERATE_9600 (0x6 << 3) /* 9.6 or 8.82 kHz */
119 #define SAMPLERATE_8000 (0x7 << 3) /* 8 or 7.35 kHz */
172 #define RATE_48000 (0x0 << 8) /* 48 kHz */
173 #define RATE_44100 (0x0 << 8) /* 44.1 kHz */
[all …]
/openbmc/linux/include/sound/
H A Dasoundef.h27 #define IEC958_AES0_PRO_FS_44100 (1<<6) /* 44.1kHz */
28 #define IEC958_AES0_PRO_FS_48000 (2<<6) /* 48kHz */
29 #define IEC958_AES0_PRO_FS_32000 (3<<6) /* 32kHz */
114 #define IEC958_AES3_CON_FS_44100 (0<<0) /* 44.1kHz */
116 #define IEC958_AES3_CON_FS_48000 (2<<0) /* 48kHz */
117 #define IEC958_AES3_CON_FS_32000 (3<<0) /* 32kHz */
118 #define IEC958_AES3_CON_FS_22050 (4<<0) /* 22.05kHz */
119 #define IEC958_AES3_CON_FS_24000 (6<<0) /* 24kHz */
120 #define IEC958_AES3_CON_FS_88200 (8<<0) /* 88.2kHz */
121 #define IEC958_AES3_CON_FS_768000 (9<<0) /* 768kHz */
[all …]
H A Demu10k1.h209 #define HCFG_BAUD_RATE 0x00080000 /* 0 = 48kHz, 1 = 44.1kHz */
630 #define ADCCR_SAMPLERATE_48 0x00000000 /* 48kHz sample rate */
631 #define ADCCR_SAMPLERATE_44 0x00000001 /* 44.1kHz sample rate */
632 #define ADCCR_SAMPLERATE_32 0x00000002 /* 32kHz sample rate */
633 #define ADCCR_SAMPLERATE_24 0x00000003 /* 24kHz sample rate */
634 #define ADCCR_SAMPLERATE_22 0x00000004 /* 22.05kHz sample rate */
635 #define ADCCR_SAMPLERATE_16 0x00000005 /* 16kHz sample rate */
636 #define ADCCR_SAMPLERATE_11 0x00000006 /* 11.025kHz sample rate */
637 #define ADCCR_SAMPLERATE_8 0x00000007 /* 8kHz sample rate */
638 #define A_ADCCR_SAMPLERATE_12 0x00000006 /* 12kHz sample rate */
[all …]
H A Ddesignware_i2s.h16 * @sample_rate: sampling frequency (8Khz, 16Khz, 32Khz, 44Khz, 48Khz)
/openbmc/linux/Documentation/devicetree/bindings/sound/
H A Dti,j721e-cpb-audio.yaml18 In order to support 48KHz and 44.1KHz family of sampling rates the parent
19 clock for AUDIO_REFCLK2 needs to be changed between PLL4 (for 48KHz) and
20 PLL15 (for 44.1KHz). The same PLLs are used for McASP10's AUXCLK clock via
24 48KHz family:
28 44.1KHz family:
33 48KHz family:
85 - description: Parent for CPB_McASP auxclk (for 48KHz)
86 - description: Parent for CPB_McASP auxclk (for 44.1KHz)
88 - description: Parent for CPB_SCKI clock (for 48KHz)
89 - description: Parent for CPB_SCKI clock (for 44.1KHz)
[all …]
H A Dti,j721e-cpb-ivi-audio.yaml23 In order to support 48KHz and 44.1KHz family of sampling rates the parent clock
24 for AUDIO_REFCLK0 needs to be changed between PLL4 (for 48KHz) and PLL15 (for
25 44.1KHz). The same PLLs are used for McASP0's AUXCLK clock via different
30 Clocking setup for 48KHz family:
37 Clocking setup for 44.1KHz family:
76 - description: Parent for CPB_McASP auxclk (for 48KHz)
77 - description: Parent for CPB_McASP auxclk (for 44.1KHz)
79 - description: Parent for CPB_SCKI clock (for 48KHz)
80 - description: Parent for CPB_SCKI clock (for 44.1KHz)
82 - description: Parent for IVI_McASP auxclk (for 48KHz)
[all …]
/openbmc/linux/drivers/gpu/drm/amd/display/include/
H A Dgrph_object_ctrl_defs.h128 uint32_t pixel_clk; /* in KHz */
160 uint32_t crystal_frequency; /* in KHz */
161 uint32_t min_input_pxl_clk_pll_frequency; /* in KHz */
162 uint32_t max_input_pxl_clk_pll_frequency; /* in KHz */
163 uint32_t min_output_pxl_clk_pll_frequency; /* in KHz */
164 uint32_t max_output_pxl_clk_pll_frequency; /* in KHz */
172 uint32_t default_display_engine_pll_frequency; /* in KHz */
173 uint32_t external_clock_source_frequency_for_dp; /* in KHz */
174 uint32_t smu_gpu_pll_output_freq; /* in KHz */
177 uint32_t default_memory_clk; /* in KHz */
[all …]
/openbmc/linux/tools/testing/selftests/alsa/
H A Dpcm-test.conf2 description "8kHz mono large periods"
11 description "8kHz stereo large periods"
20 description "44.1kHz stereo large periods"
29 description "48kHz stereo small periods"
38 description "48kHz stereo large periods"
47 description "48kHz 6 channel large periods"
56 description "96kHz stereo large periods"
/openbmc/u-boot/arch/arm/include/asm/arch-rockchip/
H A Dcru_rk3399.h70 #define KHz 1000 macro
88 #define PERIHP_ACLK_HZ (148500*KHz)
89 #define PERIHP_HCLK_HZ (148500*KHz)
90 #define PERIHP_PCLK_HZ (37125*KHz)
92 #define PERILP0_ACLK_HZ (99000*KHz)
93 #define PERILP0_HCLK_HZ (99000*KHz)
94 #define PERILP0_PCLK_HZ (49500*KHz)
96 #define PERILP1_HCLK_HZ (99000*KHz)
97 #define PERILP1_PCLK_HZ (49500*KHz)
/openbmc/linux/Documentation/devicetree/bindings/clock/
H A Dlpc1850-creg-clk.txt5 32 kHz oscillator driver with power up/down and clock gating. Next
6 is a fixed divider that creates a 1 kHz clock from the 32 kHz osc.
9 The 32 kHz can also be routed to other peripherals to enable low
21 Shall contain a phandle to the fixed 32 kHz crystal.
28 0 1 kHz clock
29 1 32 kHz Oscillator
/openbmc/linux/drivers/video/fbdev/core/
H A Dmodedb.c38 /* 640x400 @ 70 Hz, 31.5 kHz hsync */
42 /* 640x480 @ 60 Hz, 31.5 kHz hsync */
46 /* 800x600 @ 56 Hz, 35.15 kHz hsync */
50 /* 1024x768 @ 87 Hz interlaced, 35.5 kHz hsync */
54 /* 640x400 @ 85 Hz, 37.86 kHz hsync */
58 /* 640x480 @ 72 Hz, 36.5 kHz hsync */
62 /* 640x480 @ 75 Hz, 37.50 kHz hsync */
66 /* 800x600 @ 60 Hz, 37.8 kHz hsync */
71 /* 640x480 @ 85 Hz, 43.27 kHz hsync */
75 /* 1152x864 @ 89 Hz interlaced, 44 kHz hsync */
[all …]
/openbmc/u-boot/drivers/i2c/
H A Daspeed_i2c_global.c30 * I2CG10[23:16] base clk3 for Standard-mode (100Khz) min tBuf 4.7us
31 * 0x3c : 100.8Khz : 3.225Mhz : 4.96us
32 * 0x3d : 99.2Khz : 3.174Mhz : 5.04us
33 * 0x3e : 97.65Khz : 3.125Mhz : 5.12us
34 * 0x40 : 97.75Khz : 3.03Mhz : 5.28us
35 * 0x41 : 99.5Khz : 2.98Mhz : 5.36us (default)
36 * I2CG10[15:8] base clk2 for Fast-mode (400Khz) min tBuf 1.3us
37 * 0x12 : 400Khz : 10Mhz : 1.6us
/openbmc/linux/drivers/gpu/drm/nouveau/nvkm/subdev/clk/
H A Dnv40.c47 u32 ref = 27000, khz = 0; in read_pll_1() local
50 khz = ref * N / M; in read_pll_1()
52 return khz >> P; in read_pll_1()
66 u32 ref = 27000, khz = 0; in read_pll_2() local
69 khz = ref * N1 / M1; in read_pll_2()
72 khz = khz * N2 / M2; in read_pll_2()
74 khz = 0; in read_pll_2()
78 return khz >> P; in read_pll_2()
124 nv40_clk_calc_pll(struct nv40_clk *clk, u32 reg, u32 khz, in nv40_clk_calc_pll() argument
135 if (khz < pll.vco1.max_freq) in nv40_clk_calc_pll()
[all …]
/openbmc/linux/drivers/media/dvb-frontends/
H A Dtda8261.h12 TDA8261_STEP_2000 = 0, /* 2000 kHz */
13 TDA8261_STEP_1000, /* 1000 kHz */
14 TDA8261_STEP_500, /* 500 kHz */
15 TDA8261_STEP_250, /* 250 kHz */
16 TDA8261_STEP_125 /* 125 kHz */
/openbmc/openbmc/poky/meta/recipes-graphics/xorg-xserver/xserver-xf86-config/qemux86-64/
H A Dxorg.conf8 # 1024x600 59.85 Hz (CVT) hsync: 37.35 kHz; pclk: 49.00 MHz
10 # 640x480 @ 60Hz (Industry standard) hsync: 31.5kHz
12 # 640x480 @ 72Hz (VESA) hsync: 37.9kHz
14 # 640x480 @ 75Hz (VESA) hsync: 37.5kHz
16 # 640x480 @ 85Hz (VESA) hsync: 43.3kHz
/openbmc/openbmc/poky/meta/recipes-graphics/xorg-xserver/xserver-xf86-config/qemuarm/
H A Dxorg.conf13 # 1024x600 59.85 Hz (CVT) hsync: 37.35 kHz; pclk: 49.00 MHz
15 # 640x480 @ 60Hz (Industry standard) hsync: 31.5kHz
17 # 640x480 @ 72Hz (VESA) hsync: 37.9kHz
19 # 640x480 @ 75Hz (VESA) hsync: 37.5kHz
21 # 640x480 @ 85Hz (VESA) hsync: 43.3kHz
/openbmc/openbmc/poky/meta/recipes-graphics/xorg-xserver/xserver-xf86-config/qemuppc/
H A Dxorg.conf13 # 1024x600 59.85 Hz (CVT) hsync: 37.35 kHz; pclk: 49.00 MHz
15 # 640x480 @ 60Hz (Industry standard) hsync: 31.5kHz
17 # 640x480 @ 72Hz (VESA) hsync: 37.9kHz
19 # 640x480 @ 75Hz (VESA) hsync: 37.5kHz
21 # 640x480 @ 85Hz (VESA) hsync: 43.3kHz
/openbmc/openbmc/poky/meta/recipes-graphics/xorg-xserver/xserver-xf86-config/qemush4/
H A Dxorg.conf13 # 1024x600 59.85 Hz (CVT) hsync: 37.35 kHz; pclk: 49.00 MHz
15 # 640x480 @ 60Hz (Industry standard) hsync: 31.5kHz
17 # 640x480 @ 72Hz (VESA) hsync: 37.9kHz
19 # 640x480 @ 75Hz (VESA) hsync: 37.5kHz
21 # 640x480 @ 85Hz (VESA) hsync: 43.3kHz
/openbmc/openbmc/poky/meta/recipes-graphics/xorg-xserver/xserver-xf86-config/qemux86/
H A Dxorg.conf8 # 1024x600 59.85 Hz (CVT) hsync: 37.35 kHz; pclk: 49.00 MHz
10 # 640x480 @ 60Hz (Industry standard) hsync: 31.5kHz
12 # 640x480 @ 72Hz (VESA) hsync: 37.9kHz
14 # 640x480 @ 75Hz (VESA) hsync: 37.5kHz
16 # 640x480 @ 85Hz (VESA) hsync: 43.3kHz
/openbmc/linux/sound/firewire/dice/
H A Ddice-weiss.c13 // Weiss DAC202: 192kHz 2-channel DAC
19 // Weiss MAN301: 192kHz 2-channel music archive network player
25 // Weiss INT202: 192kHz unidirectional 2-channel digital Firewire nterface
31 // Weiss INT203: 192kHz bidirectional 2-channel digital Firewire nterface
37 // Weiss ADC2: 192kHz A/D converter with microphone preamps and line nputs
43 // Weiss DAC2/Minerva: 192kHz 2-channel DAC
49 // Weiss Vesta: 192kHz 2-channel Firewire to AES/EBU interface
55 // Weiss AFI1: 192kHz 24-channel Firewire to ADAT or AES/EBU interface
/openbmc/linux/Documentation/sound/cards/
H A Daudiophile-usb.rst48 * sample rate from 8kHz to 96kHz
57 * 16-bit/48kHz ==> 4 channels in + 4 channels out
61 * 24-bit/48kHz ==> 4 channels in + 2 channels out,
66 * 24-bit/96kHz ==> 2 channels in _or_ 2 channels out (half duplex only)
197 - 16bits 48kHz mode with Di disabled
204 - 16bits 48kHz mode with Di enabled
234 - 24bits 48kHz mode with Di disabled
241 - 24bits 48kHz mode with Di enabled
249 - 24bits 96kHz mode
266 - 16bits 48kHz mode with only the Do port enabled
[all …]
/openbmc/linux/Documentation/i2c/busses/
H A Di2c-ismt.rst21 Specify the bus speed in kHz.
27 80 kHz
28 100 kHz
29 400 kHz
30 1000 kHz
/openbmc/openbmc/meta-openembedded/meta-oe/recipes-support/fbset/fbset-modes/om-gta01/
H A Dfb.modes4 # D: 26.000 MHz, H: 43.334 kHz, V: 65.657 Hz
11 # D: 26.000 MHz, H: 43.334 kHz, V: 65.657 Hz
18 # D: 8.475 MHz, H: 24.635 kHz, V: 75.569 Hz
25 # D: 8.475 MHz, H: 24.635 kHz, V: 75.569 Hz
/openbmc/linux/include/linux/
H A Dclocksource.h165 * clocksource_khz2mult - calculates mult from khz and shift
166 * @khz: Clocksource frequency in KHz
169 * Helper functions that converts a khz counter frequency to a timsource
172 static inline u32 clocksource_khz2mult(u32 khz, u32 shift_constant) in clocksource_khz2mult() argument
174 return clocksource_freq2mult(khz, shift_constant, NSEC_PER_MSEC); in clocksource_khz2mult()
228 * clocksource_register_hz/khz
249 static inline int clocksource_register_khz(struct clocksource *cs, u32 khz) in clocksource_register_khz() argument
251 return __clocksource_register_scale(cs, 1000, khz); in clocksource_register_khz()
259 static inline void __clocksource_update_freq_khz(struct clocksource *cs, u32 khz) in __clocksource_update_freq_khz() argument
261 __clocksource_update_freq_scale(cs, 1000, khz); in __clocksource_update_freq_khz()

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