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/openbmc/linux/Documentation/devicetree/bindings/phy/
H A Dqcom,usb-hsic-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/qcom,usb-hsic-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm USB HSIC PHY Controller
10 - Bjorn Andersson <andersson@kernel.org>
11 - Vinod Koul <vkoul@kernel.org>
16 - enum:
17 - qcom,usb-hsic-phy-mdm9615
18 - qcom,usb-hsic-phy-msm8974
[all …]
H A Dallwinner,sun9i-a80-usb-phy.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/phy/allwinner,sun9i-a80-usb-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
14 "#phy-cells":
15 const: 0
18 const: allwinner,sun9i-a80-usb-phy
25 - maxItems: 1
[all …]
H A Dmarvell,mmp3-hsic-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/phy/marvell,mmp3-hsic-phy.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Marvell MMP3 HSIC PHY
11 - Lubomir Rintel <lkundrak@v3.sk>
15 const: marvell,mmp3-hsic-phy
21 "#phy-cells":
22 const: 0
25 - compatible
[all …]
H A Dnvidia,tegra186-xusb-padctl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra186-xusb-padctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
22 super-speed USB. Other lanes are for various types of low-speed, full-speed
23 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
24 contains a software-configurable mux that sits between the I/O controller
[all …]
H A Dnvidia,tegra124-xusb-padctl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra124-xusb-padctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
22 super-speed USB. Other lanes are for various types of low-speed, full-speed
23 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
24 contains a software-configurable mux that sits between the I/O controller
[all …]
H A Dnvidia,tegra210-xusb-padctl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra210-xusb-padctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
22 super-speed USB. Other lanes are for various types of low-speed, full-speed
23 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
24 contains a software-configurable mux that sits between the I/O controller
[all …]
H A Dpxa1928-usb-phy.txt1 * Marvell PXA1928 USB and HSIC PHYs
4 - compatible: "marvell,pxa1928-usb-phy" or "marvell,pxa1928-hsic-phy"
5 - reg: base address and length of the registers
6 - clocks - A single clock. From common clock binding.
7 - #phys-cells: should be 0. From common phy binding.
8 - resets: reference to the reset controller
13 compatible = "marvell,pxa1928-usb-phy";
14 reg = <0x7000 0xe0>;
16 #phy-cells = <0>;
/openbmc/linux/drivers/phy/samsung/
H A Dphy-exynos5250-usb2.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Samsung SoC USB 1.1/2.0 PHY driver - Exynos 5250 support
13 #include "phy-samsung-usb2.h"
16 #define EXYNOS_5250_REFCLKSEL_CRYSTAL 0x0
17 #define EXYNOS_5250_REFCLKSEL_XO 0x1
18 #define EXYNOS_5250_REFCLKSEL_CLKCORE 0x2
20 #define EXYNOS_5250_FSEL_9MHZ6 0x0
21 #define EXYNOS_5250_FSEL_10MHZ 0x1
22 #define EXYNOS_5250_FSEL_12MHZ 0x2
23 #define EXYNOS_5250_FSEL_19MHZ2 0x3
[all …]
/openbmc/linux/Documentation/devicetree/bindings/mfd/
H A Domap-usb-host.txt5 - compatible: should be "ti,usbhs-host"
6 - reg: should contain one register range i.e. start and length
7 - ti,hwmods: must contain "usb_host_hs"
11 - num-ports: number of USB ports. Usually this is automatically detected
15 - portN-mode: String specifying the port mode for port N, where N can be
18 "ehci-phy",
19 "ehci-tll",
20 "ehci-hsic",
21 "ohci-phy-6pin-datse0",
22 "ohci-phy-6pin-dpdm",
[all …]
/openbmc/linux/drivers/phy/tegra/
H A Dxusb-tegra124.c1 // SPDX-License-Identifier: GPL-2.0-only
21 #define FUSE_SKU_CALIB_HS_CURR_LEVEL_PADX_SHIFT(x) ((x) ? 15 : 0)
22 #define FUSE_SKU_CALIB_HS_CURR_LEVEL_PAD_MASK 0x3f
24 #define FUSE_SKU_CALIB_HS_IREF_CAP_MASK 0x3
26 #define FUSE_SKU_CALIB_HS_SQUELCH_LEVEL_MASK 0x3
28 #define FUSE_SKU_CALIB_HS_TERM_RANGE_ADJ_MASK 0xf
30 #define XUSB_PADCTL_USB2_PORT_CAP 0x008
32 #define XUSB_PADCTL_USB2_PORT_CAP_PORT_CAP_MASK 0x3
33 #define XUSB_PADCTL_USB2_PORT_CAP_DISABLED 0x0
34 #define XUSB_PADCTL_USB2_PORT_CAP_HOST 0x1
[all …]
H A Dxusb.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2014-2022, NVIDIA CORPORATION. All rights reserved.
31 if (args->args_count != 0) in tegra_xusb_pad_of_xlate()
32 return ERR_PTR(-EINVAL); in tegra_xusb_pad_of_xlate()
34 for (i = 0; i < pad->soc->num_lanes; i++) { in tegra_xusb_pad_of_xlate()
35 if (!pad->lanes[i]) in tegra_xusb_pad_of_xlate()
38 if (pad->lanes[i]->dev.of_node == args->np) { in tegra_xusb_pad_of_xlate()
39 phy = pad->lanes[i]; in tegra_xusb_pad_of_xlate()
45 phy = ERR_PTR(-ENODEV); in tegra_xusb_pad_of_xlate()
53 .compatible = "nvidia,tegra124-xusb-padctl",
[all …]
H A Dxusb-tegra210.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2014-2020, NVIDIA CORPORATION. All rights reserved.
27 ((x) ? (11 + ((x) - 1) * 6) : 0)
28 #define FUSE_SKU_CALIB_HS_CURR_LEVEL_PAD_MASK 0x3f
30 #define FUSE_SKU_CALIB_HS_TERM_RANGE_ADJ_MASK 0xf
32 #define FUSE_USB_CALIB_EXT_RPD_CTRL_SHIFT 0
33 #define FUSE_USB_CALIB_EXT_RPD_CTRL_MASK 0x1f
35 #define XUSB_PADCTL_USB2_PAD_MUX 0x004
37 #define XUSB_PADCTL_USB2_PAD_MUX_HSIC_PAD_TRK_MASK 0x3
38 #define XUSB_PADCTL_USB2_PAD_MUX_HSIC_PAD_TRK_XUSB 0x1
[all …]
/openbmc/linux/drivers/phy/marvell/
H A Dphy-pxa-28nm-hsic.c1 // SPDX-License-Identifier: GPL-2.0-only
22 #define PHY_28NM_HSIC_CTRL 0x08
23 #define PHY_28NM_HSIC_IMPCAL_CAL 0x18
24 #define PHY_28NM_HSIC_PLL_CTRL01 0x1c
25 #define PHY_28NM_HSIC_PLL_CTRL2 0x20
26 #define PHY_28NM_HSIC_INT 0x28
29 #define PHY_28NM_HSIC_PLL_FBDIV_SHIFT 0
59 struct platform_device *pdev = mv_phy->pdev; in mv_hsic_phy_init()
60 void __iomem *base = mv_phy->base; in mv_hsic_phy_init()
63 clk_prepare_enable(mv_phy->clk); in mv_hsic_phy_init()
[all …]
H A Dphy-mmp3-hsic.c1 // SPDX-License-Identifier: GPL-2.0+
13 #define HSIC_CTRL 0x08
27 return 0; in mmp3_hsic_phy_init()
36 { .compatible = "marvell,mmp3-hsic-phy", },
43 struct device *dev = &pdev->dev; in mmp3_hsic_phy_probe()
48 base = devm_platform_get_and_ioremap_resource(pdev, 0, NULL); in mmp3_hsic_phy_probe()
65 return 0; in mmp3_hsic_phy_probe()
71 .name = "mmp3-hsic-phy",
78 MODULE_DESCRIPTION("Marvell MMP3 USB HSIC PHY Driver");
/openbmc/linux/drivers/phy/qualcomm/
H A Dphy-qcom-usb-hsic.c1 // SPDX-License-Identifier: GPL-2.0-only
10 #include <linux/pinctrl/pinctrl-state.h>
14 #define ULPI_HSIC_CFG 0x30
15 #define ULPI_HSIC_IO_CAL 0x33
29 struct ulpi *ulpi = uphy->ulpi; in qcom_usb_hsic_phy_power_on()
33 ret = clk_prepare_enable(uphy->phy_clk); in qcom_usb_hsic_phy_power_on()
37 ret = clk_prepare_enable(uphy->cal_clk); in qcom_usb_hsic_phy_power_on()
41 ret = clk_prepare_enable(uphy->cal_sleep_clk); in qcom_usb_hsic_phy_power_on()
46 ret = ulpi_write(ulpi, ULPI_HSIC_IO_CAL, 0xff); in qcom_usb_hsic_phy_power_on()
51 ret = ulpi_write(ulpi, ULPI_HSIC_CFG, 0xa8); in qcom_usb_hsic_phy_power_on()
[all …]
/openbmc/linux/drivers/usb/chipidea/
H A Dci_hdrc_msm.c1 // SPDX-License-Identifier: GPL-2.0
13 #include <linux/reset-controller.h>
19 #define HS_PHY_AHB_MODE 0x0098
21 #define HS_PHY_GENCONFIG 0x009c
24 #define HS_PHY_GENCONFIG_2 0x00a0
30 /* Vendor base starts at 0x200 beyond CI base */
31 #define HS_PHY_CTRL 0x0040
32 #define HS_PHY_SEC_CTRL 0x0078
34 #define HS_PHY_POR_ASSERT BIT(0)
44 bool hsic; member
[all …]
H A Dusbmisc_imx.c1 // SPDX-License-Identifier: GPL-2.0+
16 #define MX25_USB_PHY_CTRL_OFFSET 0x08
19 #define MX25_EHCI_INTERFACE_SINGLE_UNI (2 << 0)
20 #define MX25_EHCI_INTERFACE_DIFF_UNI (0 << 0)
21 #define MX25_EHCI_INTERFACE_MASK (0xf)
24 #define MX25_OTG_SIC_MASK (0x3 << MX25_OTG_SIC_SHIFT)
30 #define MX25_H1_SIC_MASK (0x3 << MX25_H1_SIC_SHIFT)
43 #define MX53_USB_OTG_PHY_CTRL_0_OFFSET 0x08
44 #define MX53_USB_OTG_PHY_CTRL_1_OFFSET 0x0c
45 #define MX53_USB_CTRL_1_OFFSET 0x10
[all …]
H A Dci_hdrc_imx.c1 // SPDX-License-Identifier: GPL-2.0+
81 { .compatible = "fsl,imx23-usb", .data = &imx23_usb_data},
82 { .compatible = "fsl,imx28-usb", .data = &imx28_usb_data},
83 { .compatible = "fsl,imx27-usb", .data = &imx27_usb_data},
84 { .compatible = "fsl,imx6q-usb", .data = &imx6q_usb_data},
85 { .compatible = "fsl,imx6sl-usb", .data = &imx6sl_usb_data},
86 { .compatible = "fsl,imx6sx-usb", .data = &imx6sx_usb_data},
87 { .compatible = "fsl,imx6ul-usb", .data = &imx6ul_usb_data},
88 { .compatible = "fsl,imx7d-usb", .data = &imx7d_usb_data},
89 { .compatible = "fsl,imx7ulp-usb", .data = &imx7ulp_usb_data},
[all …]
/openbmc/linux/drivers/clk/sunxi-ng/
H A Dccu-sun9i-a80-usb.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2016 Chen-Yu Tsai. All rights reserved.
7 #include <linux/clk-provider.h>
15 #include "ccu-sun9i-a80-usb.h"
25 static SUNXI_CCU_GATE_DATA(bus_hci0_clk, "bus-hci0", clk_parent_bus, 0x0, BIT(1), 0);
26 static SUNXI_CCU_GATE_DATA(usb_ohci0_clk, "usb-ohci0", clk_parent_hosc, 0x0, BIT(2), 0);
27 static SUNXI_CCU_GATE_DATA(bus_hci1_clk, "bus-hci1", clk_parent_bus, 0x0, BIT(3), 0);
28 static SUNXI_CCU_GATE_DATA(bus_hci2_clk, "bus-hci2", clk_parent_bus, 0x0, BIT(5), 0);
29 static SUNXI_CCU_GATE_DATA(usb_ohci2_clk, "usb-ohci2", clk_parent_hosc, 0x0, BIT(6), 0);
31 static SUNXI_CCU_GATE_DATA(usb0_phy_clk, "usb0-phy", clk_parent_hosc, 0x4, BIT(1), 0);
[all …]
/openbmc/linux/drivers/pinctrl/tegra/
H A Dpinctrl-tegra-xusb.c1 // SPDX-License-Identifier: GPL-2.0-only
20 #include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>
23 #include "../pinctrl-utils.h"
25 #define XUSB_PADCTL_ELPG_PROGRAM 0x01c
30 #define XUSB_PADCTL_IOPHY_PLL_P0_CTL1 0x040
32 #define XUSB_PADCTL_IOPHY_PLL_P0_CTL1_REFCLK_SEL_MASK (0xf << 12)
35 #define XUSB_PADCTL_IOPHY_PLL_P0_CTL2 0x044
40 #define XUSB_PADCTL_IOPHY_PLL_S0_CTL1 0x138
45 #define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_IDDQ (1 << 0)
47 #define XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1 0x148
[all …]
/openbmc/linux/drivers/gpu/drm/bridge/
H A Dsil-sii8620.h1 /* SPDX-License-Identifier: GPL-2.0-only */
9 * Copyright (C) 2013-2014 Silicon Image, Inc.
15 /* Vendor ID Low byte, default value: 0x01 */
16 #define REG_VND_IDL 0x0000
18 /* Vendor ID High byte, default value: 0x00 */
19 #define REG_VND_IDH 0x0001
21 /* Device ID Low byte, default value: 0x60 */
22 #define REG_DEV_IDL 0x0002
24 /* Device ID High byte, default value: 0x86 */
25 #define REG_DEV_IDH 0x0003
[all …]
/openbmc/linux/Documentation/devicetree/bindings/pinctrl/
H A Dqcom,msm8974-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/qcom,msm8974-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bjorn Andersson <andersson@kernel.org>
11 - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
18 const: qcom,msm8974-pinctrl
26 interrupt-controller: true
27 "#interrupt-cells": true
28 gpio-controller: true
[all …]
H A Dnvidia,tegra124-xusb-padctl.txt7 needed for USB. For the new binding, see ../phy/nvidia,tegra-xusb-padctl.txt.
14 This document defines the device-specific binding for the XUSB pad controller.
16 Refer to pinctrl-bindings.txt in this directory for generic information about
17 pin controller device tree bindings and ../phy/phy-bindings.txt for details on
21 --------------------
22 - compatible: For Tegra124, must contain "nvidia,tegra124-xusb-padctl".
23 Otherwise, must contain '"nvidia,<chip>-xusb-padctl",
24 "nvidia-tegra124-xusb-padctl"', where <chip> is tegra132 or tegra210.
25 - reg: Physical base address and length of the controller's registers.
26 - resets: Must contain an entry for each entry in reset-names.
[all …]
/openbmc/linux/Documentation/devicetree/bindings/usb/
H A Dci-hdrc-usb2.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/usb/ci-hdrc-usb2.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Xu Yang <xu.yang_2@nxp.com>
11 - Peng Fan <peng.fan@nxp.com>
16 - enum:
17 - chipidea,usb2
18 - lsi,zevio-usb
19 - nuvoton,npcm750-udc
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-sunxi/
H A Dclock_sun50i_h6.h6 * SPDX-License-Identifier: GPL-2.0+
13 u32 pll1_cfg; /* 0x000 pll1 (cpux) control */
15 u32 pll5_cfg; /* 0x010 pll5 (ddr) control */
17 u32 pll6_cfg; /* 0x020 pll6 (periph0) control */
19 u32 pll_periph1_cfg; /* 0x028 pll periph1 control */
21 u32 pll7_cfg; /* 0x030 pll7 (gpu) control */
23 u32 pll3_cfg; /* 0x040 pll3 (video0) control */
25 u32 pll_video1_cfg; /* 0x048 pll video1 control */
27 u32 pll4_cfg; /* 0x058 pll4 (ve) control */
29 u32 pll10_cfg; /* 0x060 pll10 (de) control */
[all …]

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