Searched full:cpll (Results 1 – 13 of 13) sorted by relevance
| /openbmc/u-boot/arch/m68k/cpu/mcf52x2/ |
| H A D | speed.c | 28 volatile unsigned long cpll = mbar2_readLong(MCFSIM_PLLCR); in get_clocks() local
46 cpll = cpll & 0xfffffffe; /* Set PLL bypass mode = 0 (PSTCLK = crystal) */ in get_clocks()
47 mbar2_writeLong(MCFSIM_PLLCR, cpll); /* Set the PLL to bypass mode (PSTCLK = crystal) */ in get_clocks()
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| /openbmc/u-boot/drivers/clk/rockchip/ |
| H A D | clk_rk3368.c | 132 u32 apllb, aplll, dpll, cpll, gpll; in rkclk_init() local
142 rkclk_set_pll(cru, CPLL, &cpll_init_cfg); in rkclk_init()
148 cpll = rkclk_pll_get_rate(cru, CPLL); in rkclk_init()
151 debug("%s apllb(%d) apll(%d) dpll(%d) cpll(%d) gpll(%d)\n", in rkclk_init()
152 __func__, apllb, aplll, dpll, cpll, gpll); in rkclk_init()
185 pll_rate = rkclk_pll_get_rate(cru, CPLL); in rk3368_mmc_get_clk()
335 /* CPLL is not set */ in rk3368_gmac_set_clk()
354 * to select either CPLL or GPLL as the clock-parent. The location within
460 rate = rkclk_pll_get_rate(priv->cru, CPLL); in rk3368_clk_get_rate()
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| H A D | clk_rk3399.c | 595 * to select either CPLL or GPLL as the clock-parent. The location within
697 /* vop aclk source clk: cpll */ in rk3399_vop_set_clk()
1112 /* configure gpll cpll */ in rkclk_init()
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| H A D | clk_rk322x.c | 258 /* CPLL is not set */ in rk322x_mac_set_clk()
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| H A D | clk_rk3328.c | 285 /* configure gpll cpll */ in rkclk_init()
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| H A D | clk_rk3288.c | 841 /* vop aclk source clk: cpll */ in rk3288_clk_set_rate()
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| /openbmc/u-boot/arch/arm/mach-uniphier/clk/ |
| H A D | pll-ld11.c | 43 writel(0, SC_CA53_GEARSET); /* Gear0: CPLL/2 */ in uniphier_ld11_pll_init()
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| /openbmc/u-boot/arch/arm/mach-exynos/include/mach/ |
| H A D | clk.h | 18 #define CPLL 8 macro
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| /openbmc/u-boot/arch/arm/include/asm/arch-rockchip/ |
| H A D | cru_rk3368.h | 17 CPLL, enumerator
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| /openbmc/u-boot/arch/mips/mach-mt7620/ |
| H A D | lowlevel_init.S | 70 /* polling CPLL is ready */
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| /openbmc/u-boot/arch/arm/mach-rockchip/ |
| H A D | rk3288-board.c | 279 { "cpll", CLK_CODEC }, in do_clock()
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| /openbmc/u-boot/arch/arm/mach-exynos/ |
| H A D | clock_init_exynos5.c | 147 /* CPLL @666MHz */
639 /* Set CPLL */ in exynos5250_system_clock_init()
868 /* Set CPLL */ in exynos5420_system_clock_init()
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| H A D | clock.c | 1049 const int reg_map[] = {0, CPLL, DPLL, MPLL, SPLL, IPLL, EPLL, in exynos5800_get_lcd_clk()
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