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Searched full:corepll (Results 1 – 10 of 10) sorted by relevance

/openbmc/u-boot/board/freescale/common/
H A Dpixis.c120 static int set_px_corepll(unsigned long corepll) in set_px_corepll() argument
124 switch (corepll) { in set_px_corepll()
144 printf("Unsupported COREPLL ratio.\n"); in set_px_corepll()
156 /* Tell the PIXIS where to find the COREPLL, MPXPLL, SYSCLK values
159 * or various other PIXIS registers to determine the values for COREPLL,
388 /* Currently needed only for single digit corepll ratios */ in strfractoint()
487 unsigned long corepll; in pixis_reset_cmd() local
491 corepll = strfractoint(p_cf_corepll); in pixis_reset_cmd()
495 && set_px_corepll(corepll) in pixis_reset_cmd()
539 " pixis_reset altbank cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>\n"
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/openbmc/u-boot/board/freescale/mpc8610hpcd/
H A DREADME50 pixis_reset altbank cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>
51 pixis_reset cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>
65 * 40 is SYSCLK, 2.5 is COREPLL ratio, 10 is MPXPLL ratio
/openbmc/u-boot/board/freescale/mpc8544ds/
H A DREADME68 pixis_reset altbank cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>
69 pixis_reset cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>
83 * 40 is SYSCLK, 2.5 is COREPLL ratio, 10 is MPXPLL ratio
/openbmc/u-boot/board/freescale/mpc8641hpcn/
H A DREADME167 pixis_reset altbank cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>
168 pixis_reset cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>
182 * 40 is SYSCLK, 2.5 is COREPLL ratio, 10 is MPXPLL ratio
/openbmc/u-boot/board/freescale/mpc8572ds/
H A DREADME62 pixis_reset altbank cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>
63 pixis_reset cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>
/openbmc/u-boot/arch/arm/include/asm/arch-owl/
H A Dclk_s900.h39 /* COREPLL register definitions */
/openbmc/u-boot/drivers/clk/
H A Dmpc83xx_clk.c190 u8 corepll = spmr_field(im, SPMR_COREPLL); in init_single_clk() local
191 u32 corecnf_tab_index = ((corepll & 0x1F) << 2) | in init_single_clk()
192 ((corepll & 0x60) >> 5); in init_single_clk()
H A Dmpc83xx_clk.h45 * indexed by the COREPLL field of the SPMR
/openbmc/u-boot/arch/powerpc/cpu/mpc83xx/
H A Dspeed.c84 u8 corepll; in get_clocks() local
408 corepll = (im->clk.spmr & SPMR_COREPLL) >> SPMR_COREPLL_SHIFT; in get_clocks()
415 corecnf_tab_index = ((corepll & 0x1F) << 2) | ((corepll & 0x60) >> 5); in get_clocks()
/openbmc/u-boot/drivers/clk/sifive/
H A Dfu540-prci.c382 * __prci_coreclksel_use_corepll() - switch the CORECLK mux to output COREPLL
505 .name = "corepll",
524 .parent_name = "corepll",