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/openbmc/u-boot/arch/arc/dts/
H A Daxc001.dtsi10 core_clk: core_clk { label
H A Daxc003.dtsi10 core_clk: core_clk { label
H A Dnsim.dts17 core_clk: core_clk { label
H A Dabilis_tb100.dts17 core_clk: core_clk { label
H A Demsdp.dts20 core_clk: core_clk { label
H A Diot_devkit.dts18 core_clk: core_clk { label
H A Dhsdk.dts22 core_clk: core_clk { label
H A Dskeleton.dtsi21 clocks = <&core_clk>;
/openbmc/u-boot/doc/device-tree-bindings/timer/
H A Darc_timer.txt13 clocks = <&core_clk>;
19 clocks = <&core_clk>;
/openbmc/u-boot/arch/powerpc/cpu/mpc83xx/
H A Dspeed.c99 u32 core_clk; in get_clocks() local
424 core_clk = csb_clk; in get_clocks()
427 core_clk = (3 * csb_clk) / 2; in get_clocks()
430 core_clk = 2 * csb_clk; in get_clocks()
433 core_clk = (5 * csb_clk) / 2; in get_clocks()
436 core_clk = 3 * csb_clk; in get_clocks()
468 gd->arch.core_clk = core_clk; in get_clocks()
495 gd->cpu_clk = gd->arch.core_clk; in get_clocks()
525 strmhz(buf, gd->arch.core_clk)); in do_clocks()
H A Dfdt.c103 "clock-frequency", gd->arch.core_clk, 1); in ft_cpu_setup()
/openbmc/u-boot/arch/powerpc/include/asm/
H A Dglobal_data.h34 u32 core_clk; member
52 u32 core_clk; member
/openbmc/u-boot/arch/arm/dts/
H A Dkirkwood.dtsi20 clocks = <&core_clk 1>, <&core_clk 3>, <&gate_clk 11>;
121 core_clk: core-clocks@10030 { label
221 clocks = <&core_clk 0>;
242 clocks = <&core_clk 0>;
/openbmc/u-boot/drivers/cpu/
H A Dmpc83xx_cpu.c242 struct clk core_clk; in mpc83xx_cpu_get_desc() local
248 ret = clk_get_by_index(dev, 0, &core_clk); in mpc83xx_cpu_get_desc()
272 strmhz(core_freq, clk_get_rate(&core_clk)), in mpc83xx_cpu_get_desc()
/openbmc/u-boot/drivers/clk/renesas/
H A Drenesas-cpg-mssr.c94 if (info->core_clk[i].id != clkid) in renesas_clk_get_core()
97 *core = &info->core_clk[i]; in renesas_clk_get_core()
H A Drenesas-cpg-mssr.h17 const struct cpg_core_clk *core_clk; member
H A Dr8a7796-cpg-mssr.c311 .core_clk = r8a7796_core_clks,
326 .core_clk = r8a7796_core_clks,
H A Dr8a77970-cpg-mssr.c202 .core_clk = r8a77970_core_clks,
H A Dr8a7792-cpg-mssr.c210 .core_clk = r8a7792_core_clks,
H A Dr8a77995-cpg-mssr.c216 .core_clk = r8a77995_core_clks,
/openbmc/u-boot/drivers/clk/owl/
H A Dclk_s900.c51 /* Source CORE_PLL for CORE_CLK */ in owl_clk_init()
/openbmc/u-boot/drivers/adc/
H A Dmeson-saradc.c172 struct clk core_clk; member
583 ret = clk_enable(&priv->core_clk); in meson_saradc_init()
662 ret = clk_get_by_name(dev, "core", &priv->core_clk); in meson_saradc_probe()
/openbmc/u-boot/board/synopsys/iot_devkit/
H A Diot_devkit.c128 offset = fdt_path_offset(gd->fdt_blob, "/cpu_card/core_clk"); in mach_cpu_init()
/openbmc/u-boot/arch/arm/cpu/armv8/s32v234/
H A Dgeneric.c115 /* ARMPLL has as source XOSC and CORE_CLK has as input PHI0 */ in get_mcu_main_clk()
/openbmc/u-boot/board/freescale/s32v234evb/
H A Dclock.c191 /* setup the sys clock divider for CORE_CLK (1000MHz) */ in setup_sys_clocks()

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