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Searched full:clksel (Results 1 – 25 of 44) sorted by relevance

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/openbmc/linux/drivers/mmc/host/
H A Ddw_mmc-exynos.c92 return SDMMC_CLKSEL_GET_DIV(mci_readl(host, CLKSEL)) + 1; in dw_mci_exynos_get_ciu_div()
143 u32 clksel; in dw_mci_exynos_set_clksel_timing() local
148 clksel = mci_readl(host, CLKSEL64); in dw_mci_exynos_set_clksel_timing()
150 clksel = mci_readl(host, CLKSEL); in dw_mci_exynos_set_clksel_timing()
152 clksel = (clksel & ~SDMMC_CLKSEL_TIMING_MASK) | timing; in dw_mci_exynos_set_clksel_timing()
157 mci_writel(host, CLKSEL64, clksel); in dw_mci_exynos_set_clksel_timing()
159 mci_writel(host, CLKSEL, clksel); in dw_mci_exynos_set_clksel_timing()
168 if (!SDMMC_CLKSEL_GET_DRV_WD3(clksel) && host->slot) in dw_mci_exynos_set_clksel_timing()
207 * WAKEUP_INT bit in the CLKSEL register asserted. This bit is 1 to indicate
217 u32 clksel; in dw_mci_exynos_resume_noirq() local
[all …]
H A Ddw_mmc-exynos.h19 /* CLKSEL register defines */
/openbmc/linux/Documentation/devicetree/bindings/clock/ti/
H A Dti,clksel.yaml4 $id: http://devicetree.org/schemas/clock/ti/ti,clksel.yaml#
7 title: TI clksel clock
13 The TI CLKSEL clocks consist of consist of input clock mux bits, and in some
18 const: ti,clksel
22 description: The CLKSEL register range
34 description: The CLKSEL register and bit offset
47 compatible = "ti,clksel";
/openbmc/linux/drivers/clk/rockchip/
H A Dclk-cpu.c105 const struct rockchip_cpuclk_clksel *clksel = &rate->divs[i]; in rockchip_cpuclk_set_dividers() local
107 if (!clksel->reg) in rockchip_cpuclk_set_dividers()
111 __func__, clksel->reg, clksel->val); in rockchip_cpuclk_set_dividers()
112 writel(clksel->val, cpuclk->reg_base + clksel->reg); in rockchip_cpuclk_set_dividers()
123 const struct rockchip_cpuclk_clksel *clksel = &rate->pre_muxs[i]; in rockchip_cpuclk_set_pre_muxs() local
125 if (!clksel->reg) in rockchip_cpuclk_set_pre_muxs()
129 __func__, clksel->reg, clksel->val); in rockchip_cpuclk_set_pre_muxs()
130 writel(clksel->val, cpuclk->reg_base + clksel->reg); in rockchip_cpuclk_set_pre_muxs()
141 const struct rockchip_cpuclk_clksel *clksel = &rate->post_muxs[i]; in rockchip_cpuclk_set_post_muxs() local
143 if (!clksel->reg) in rockchip_cpuclk_set_post_muxs()
[all …]
/openbmc/linux/drivers/clk/
H A Dclk-milbeaut.c17 #define CLKSEL(n) (((n) - 1) * 4 + M10V_CLKSEL1) macro
254 {"emmc", M10V_PLL11, CLKSEL(1), 28, 3, emmcclk_table, 0,
256 {"mclk400", M10V_PLL1DIV2, CLKSEL(10), 7, 3, mclk400_table, 0, -1},
257 {"mclk200", M10V_PLL1DIV2, CLKSEL(10), 3, 4, mclk200_table, 0, -1},
258 {"aclk400", M10V_PLL1DIV2, CLKSEL(10), 0, 3, aclk400_table, 0, -1},
259 {"aclk300", M10V_PLL2DIV2, CLKSEL(12), 0, 2, aclk300_table, 0, -1},
260 {"aclk", M10V_PLL1DIV2, CLKSEL(9), 20, 4, aclk_table, 0, M10V_ACLK_ID},
261 {"aclkexs", M10V_PLL1DIV2, CLKSEL(9), 16, 4, aclkexs_table, 0, -1},
262 {"hclk", M10V_PLL1DIV2, CLKSEL(9), 7, 5, hclk_table, 0, M10V_HCLK_ID},
263 {"hclkbmh", M10V_PLL1DIV2, CLKSEL(9), 12, 4, hclkbmh_table, 0, -1},
[all …]
H A Dclk-qoriq.c59 struct clockgen_sourceinfo clksel[NUM_MUX_PARENTS]; member
852 u32 clksel; in mux_set_parent() local
857 clksel = hwc->parent_to_clksel[idx]; in mux_set_parent()
858 cg_out(hwc->cg, (clksel << CLKSEL_SHIFT) & CLKSEL_MASK, hwc->reg); in mux_set_parent()
866 u32 clksel; in mux_get_parent() local
869 clksel = (cg_in(hwc->cg, hwc->reg) & CLKSEL_MASK) >> CLKSEL_SHIFT; in mux_get_parent()
871 ret = hwc->clksel_to_parent[clksel]; in mux_get_parent()
873 pr_err("%s: mux at %p has bad clksel\n", __func__, hwc->reg); in mux_get_parent()
900 if (!(hwc->info->clksel[idx].flags & CLKSEL_VALID)) in get_pll_div()
903 pll = hwc->info->clksel[idx].pll; in get_pll_div()
[all …]
/openbmc/linux/arch/arm/boot/dts/ti/omap/
H A Domap36xx-omap3430es2plus-clocks.dtsi9 compatible = "ti,clksel";
24 compatible = "ti,clksel";
54 compatible = "ti,clksel";
85 compatible = "ti,clksel";
172 compatible = "ti,clksel";
194 compatible = "ti,clksel";
H A Domap34xx-omap36xx-clocks.dtsi17 compatible = "ti,clksel";
65 compatible = "ti,clksel";
105 compatible = "ti,clksel";
160 compatible = "ti,clksel";
228 compatible = "ti,clksel";
252 compatible = "ti,clksel";
H A Domap3430es1-clocks.dtsi50 compatible = "ti,clksel";
81 compatible = "ti,clksel";
121 compatible = "ti,clksel";
174 compatible = "ti,clksel";
H A Domap36xx-am35xx-omap3430es2plus-clocks.dtsi138 compatible = "ti,clksel";
153 compatible = "ti,clksel";
168 compatible = "ti,clksel";
183 compatible = "ti,clksel";
H A Domap3xxx-clocks.dtsi83 compatible = "ti,clksel";
120 compatible = "ti,clksel";
259 compatible = "ti,clksel";
429 compatible = "ti,clksel";
471 compatible = "ti,clksel";
603 compatible = "ti,clksel";
666 compatible = "ti,clksel";
709 compatible = "ti,clksel";
734 compatible = "ti,clksel";
914 compatible = "ti,clksel";
[all …]
H A Dam35xx-clocks.dtsi66 compatible = "ti,clksel";
101 compatible = "ti,clksel";
H A Dam33xx-clocks.dtsi108 compatible = "ti,clksel";
566 compatible = "ti,clksel";
571 gfx_fclk_clksel_ck: clock-gfx-fclk-clksel {
589 compatible = "ti,clksel";
H A Domap36xx-clocks.dtsi62 compatible = "ti,clksel";
/openbmc/linux/drivers/clocksource/
H A Dtimer-cadence-ttc.c476 int clksel, ret; in ttc_timer_probe() local
504 clksel = readl_relaxed(timer_baseaddr + TTC_CLK_CNTRL_OFFSET); in ttc_timer_probe()
505 clksel = !!(clksel & TTC_CLK_CNTRL_CSRC_MASK); in ttc_timer_probe()
506 clk_cs = of_clk_get(timer, clksel); in ttc_timer_probe()
512 clksel = readl_relaxed(timer_baseaddr + 4 + TTC_CLK_CNTRL_OFFSET); in ttc_timer_probe()
513 clksel = !!(clksel & TTC_CLK_CNTRL_CSRC_MASK); in ttc_timer_probe()
514 clk_ce = of_clk_get(timer, clksel); in ttc_timer_probe()
/openbmc/qemu/hw/char/
H A Domap_uart.c38 uint8_t clksel; member
47 s->clksel = 0; in omap_uart_reset()
/openbmc/u-boot/board/synopsys/iot_devkit/
H A Diot_devkit.c21 #define CLKSEL (void *)(SYSCON_BASE + 0x24) macro
40 writel(CLKSEL_DEFAULT, CLKSEL); in set_cpu_freq()
95 writel(CLKSEL_DEFAULT | BIT(0), CLKSEL); in set_cpu_freq()
/openbmc/linux/arch/arm/mach-imx/
H A Dmach-imx6q.c85 u32 clksel; in imx6q_1588_init() local
118 clksel = clk_is_match(ptp_clk, enet_ref) ? in imx6q_1588_init()
125 clksel); in imx6q_1588_init()
/openbmc/u-boot/drivers/mmc/
H A Dexynos_dw_mmc.c45 * CLKSEL register for every mmc channel.
65 * value set in the CLKSEL register, we need to use the same output in exynos_dwmci_get_clk()
122 host->clksel = exynos_dwmci_clksel; in exynos_dwmci_core_init()
/openbmc/u-boot/arch/arm/mach-exynos/include/mach/
H A Ddwmmc.h25 /* CLKSEL Register */
/openbmc/qemu/tests/qtest/
H A Dnpcm7xx_pwm-test.c41 #define CLKSEL 0x04 macro
291 uint32_t clksel = qtest_readl(qts, CLK_BA + CLKSEL); in read_pclk() local
297 switch (CPUCKSEL(clksel)) { in read_pclk()
/openbmc/u-boot/doc/device-tree-bindings/exynos/
H A Ddwmmc.txt32 'SelClk_sample', 'SelClk_drv' and 'DIVRATIO' of CLKSEL register.
/openbmc/linux/drivers/net/wireless/mediatek/mt76/mt76x0/
H A Dphy.h71 u8 pllR28_b3b2; /* clksel option */
/openbmc/linux/drivers/gpu/drm/renesas/rcar-du/
H A Drcar_lvds.c138 u32 clksel; member
143 u32 clksel, bool dot_clock_only) in rcar_lvds_d3_e3_pll_calc() argument
251 pll->clksel = clksel; in rcar_lvds_d3_e3_pll_calc()
285 lvdpllcr = LVDPLLCR_PLLON | pll.clksel | LVDPLLCR_CLKOUT in rcar_lvds_pll_setup_d3_e3()
/openbmc/linux/Documentation/devicetree/bindings/iio/adc/
H A Dti,ads131e08.yaml36 Note: clock source is selected using CLKSEL pin.

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