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/openbmc/linux/tools/perf/pmu-events/arch/x86/broadwellx/
H A Duncore-memory.json7 …"PublicDescription": "DRAM RD_CAS and WR_CAS Commands; Counts the total number of DRAM Read CAS co…
17 …"PublicDescription": "DRAM RD_CAS and WR_CAS Commands; Counts the total number of DRAM Write CAS c…
27 …number of DRAM Activate commands sent on this channel. Activate commands are issued to open up a …
36 …number of DRAM Activate commands sent on this channel. Activate commands are issued to open up a …
45 …number of DRAM Activate commands sent on this channel. Activate commands are issued to open up a …
74 … "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; All DRAM WR_CAS (w/ and w/out auto-pre)",
78 …"PublicDescription": "DRAM RD_CAS and WR_CAS Commands; Counts the total number of DRAM CAS command…
87 …"PublicDescription": "DRAM RD_CAS and WR_CAS Commands; Counts the total number of DRAM Read CAS co…
92 … "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; All DRAM RD_CAS (w/ and w/out auto-pre)",
96 …"PublicDescription": "DRAM RD_CAS and WR_CAS Commands; Counts the total number or DRAM Read CAS co…
[all …]
/openbmc/linux/tools/perf/pmu-events/arch/x86/haswellx/
H A Duncore-memory.json7 …"PublicDescription": "DRAM RD_CAS and WR_CAS Commands; Counts the total number of DRAM Read CAS co…
17 …"PublicDescription": "DRAM RD_CAS and WR_CAS Commands; Counts the total number of DRAM Write CAS c…
27 …number of DRAM Activate commands sent on this channel. Activate commands are issued to open up a …
36 …number of DRAM Activate commands sent on this channel. Activate commands are issued to open up a …
45 …number of DRAM Activate commands sent on this channel. Activate commands are issued to open up a …
74 … "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; All DRAM WR_CAS (w/ and w/out auto-pre)",
78 …"PublicDescription": "DRAM RD_CAS and WR_CAS Commands; Counts the total number of DRAM CAS command…
87 …"PublicDescription": "DRAM RD_CAS and WR_CAS Commands; Counts the total number of DRAM Read CAS co…
92 … "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; All DRAM RD_CAS (w/ and w/out auto-pre)",
96 …"PublicDescription": "DRAM RD_CAS and WR_CAS Commands; Counts the total number or DRAM Read CAS co…
[all …]
/openbmc/linux/tools/perf/pmu-events/arch/x86/broadwellde/
H A Duncore-memory.json7 …number of DRAM Activate commands sent on this channel. Activate commands are issued to open up a …
16 …number of DRAM Activate commands sent on this channel. Activate commands are issued to open up a …
25 …number of DRAM Activate commands sent on this channel. Activate commands are issued to open up a …
54 … "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; All DRAM WR_CAS (w/ and w/out auto-pre)",
58 …"PublicDescription": "DRAM RD_CAS and WR_CAS Commands; Counts the total number of DRAM CAS command…
67 …"PublicDescription": "DRAM RD_CAS and WR_CAS Commands; Counts the total number of DRAM Read CAS co…
72 … "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; All DRAM RD_CAS (w/ and w/out auto-pre)",
76 …"PublicDescription": "DRAM RD_CAS and WR_CAS Commands; Counts the total number or DRAM Read CAS co…
93 …nds; Counts the number of underfill reads that are issued by the memory controller. This will gen…
110 …"PublicDescription": "DRAM RD_CAS and WR_CAS Commands; Counts the total number of DRAM Write CAS c…
[all …]
/openbmc/linux/tools/perf/pmu-events/arch/x86/ivytown/
H A Duncore-memory.json7 …number of DRAM Activate commands sent on this channel. Activate commands are issued to open up a …
16 …number of DRAM Activate commands sent on this channel. Activate commands are issued to open up a …
25 …number of DRAM Activate commands sent on this channel. Activate commands are issued to open up a …
54 … "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; All DRAM WR_CAS (w/ and w/out auto-pre)",
58 …"PublicDescription": "DRAM RD_CAS and WR_CAS Commands; Counts the total number of DRAM CAS command…
67 …"PublicDescription": "DRAM RD_CAS and WR_CAS Commands; Counts the total number of DRAM Read CAS co…
72 … "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; All DRAM RD_CAS (w/ and w/out auto-pre)",
76 …"PublicDescription": "DRAM RD_CAS and WR_CAS Commands; Counts the total number or DRAM Read CAS co…
93 …nds; Counts the number of underfill reads that are issued by the memory controller. This will gen…
110 …"PublicDescription": "DRAM RD_CAS and WR_CAS Commands; Counts the total number of DRAM Write CAS c…
[all …]
/openbmc/linux/tools/perf/pmu-events/arch/x86/skylakex/
H A Duncore-memory.json27 …number of DRAM Activate commands sent on this channel. Activate commands are issued to open up a …
36 …number of DRAM Activate commands sent on this channel. Activate commands are issued to open up a …
121 …line back to DRAM. This event will generally count about the same as the number of partial writes,…
151 … "DRAM CAS (Column Address Strobe) Commands.; DRAM WR_CAS (w/ and w/out auto-pre) in Read Major Mo…
155 …escription": "Counts the total number of Opportunistic DRAM Write CAS commands issued on this chan…
160 … "DRAM CAS (Column Address Strobe) Commands.; DRAM WR_CAS (w/ and w/out auto-pre) in Write Major M…
164 …ublicDescription": "Counts the total number or DRAM Write CAS commands issued on this channel whil…
176 … "BriefDescription": "Clockticks in the Memory Controller using a dedicated 48-bit Fixed Counter",
187 "PublicDescription": "Counts the number of times that the precharge all command was sent.",
191 "BriefDescription": "Number of DRAM Refreshes Issued",
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/openbmc/linux/tools/testing/selftests/gpio/
H A Dgpio-sim.sh2 # SPDX-License-Identifier: GPL-2.0
6 CONFIGFS_DIR="/sys/kernel/config/gpio-sim"
7 MODULE="gpio-sim"
25 BANK=`basename $FILE`
26 if [ "$BANK" = "live" -o "$BANK" = "dev_name" ]; then
30 LINES=`ls $CONFIGFS_DIR/$CHIP/$BANK/ | grep -E ^line`
33 if [ -e $CONFIGFS_DIR/$CHIP/$BANK/$LINE/hog ]; then
34 rmdir $CONFIGFS_DIR/$CHIP/$BANK/$LINE/hog || \
38 rmdir $CONFIGFS_DIR/$CHIP/$BANK/$LINE || \
43 rmdir $CONFIGFS_DIR/$CHIP/$BANK
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/openbmc/linux/drivers/pinctrl/samsung/
H A Dpinctrl-samsung.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * pin-controller/pin-mux/pin-config/gpio-driver for Samsung's SoC's.
25 * enum pincfg_type - possible pin configuration types supported.
46 * packed together into a 16-bits. The upper 8-bits represent the configuration
47 * type and the lower 8-bits hold the value of the configuration type.
65 * enum eint_type - possible external interrupt types.
66 * @EINT_TYPE_NONE: bank does not support external interrupts
67 * @EINT_TYPE_GPIO: bank supportes external gpio interrupts
68 * @EINT_TYPE_WKUP: bank supportes external wakeup interrupts
69 * @EINT_TYPE_WKUP_MUX: bank supports multiplexed external wakeup interrupts
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/openbmc/linux/tools/perf/pmu-events/arch/x86/cascadelakex/
H A Duncore-memory.json27 …number of DRAM Activate commands sent on this channel. Activate commands are issued to open up a …
36 …number of DRAM Activate commands sent on this channel. Activate commands are issued to open up a …
121 …line back to DRAM. This event will generally count about the same as the number of partial writes,…
151 … "DRAM CAS (Column Address Strobe) Commands.; DRAM WR_CAS (w/ and w/out auto-pre) in Read Major Mo…
155 …escription": "Counts the total number of Opportunistic DRAM Write CAS commands issued on this chan…
160 … "DRAM CAS (Column Address Strobe) Commands.; DRAM WR_CAS (w/ and w/out auto-pre) in Write Major M…
164 …ublicDescription": "Counts the total number or DRAM Write CAS commands issued on this channel whil…
176 … "BriefDescription": "Clockticks in the Memory Controller using a dedicated 48-bit Fixed Counter",
187 "PublicDescription": "Counts the number of times that the precharge all command was sent.",
195 …number of ECC errors detected and corrected by the iMC on this channel. This counter is only usef…
[all …]
/openbmc/u-boot/drivers/gpio/
H A Dzynq_gpio.c1 // SPDX-License-Identifier: GPL-2.0+
7 * Most of code taken from linux kernel driver (linux/drivers/gpio/gpio-zynq.c)
8 * Copyright (C) 2009 - 2014 Xilinx, Inc.
44 ZYNQ##str##_GPIO_BANK0_NGPIO - 1)
47 ZYNQ##str##_GPIO_BANK1_NGPIO - 1)
50 ZYNQ##str##_GPIO_BANK2_NGPIO - 1)
53 ZYNQ##str##_GPIO_BANK3_NGPIO - 1)
56 ZYNQ##str##_GPIO_BANK4_NGPIO - 1)
59 ZYNQ##str##_GPIO_BANK5_NGPIO - 1)
62 /* LSW Mask & Data -WO */
[all …]
H A Dtegra_gpio.c1 // SPDX-License-Identifier: GPL-2.0+
4 * (C) Copyright 2010-2012,2015
22 #include <dm/device-internal.h>
23 #include <dt-bindings/gpio/gpio.h>
31 struct gpio_ctlr_bank *bank; member
33 int base_gpio; /* Port number for this port (0, 1,.., n-1) */
36 /* Information about each port at run-time */
38 struct gpio_ctlr_bank *bank; member
39 int base_gpio; /* Port number for this port (0, 1,.., n-1) */
46 struct gpio_ctlr_bank *bank = &ctlr->gpio_bank[GPIO_BANK(gpio)]; in get_config() local
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/openbmc/linux/Documentation/devicetree/bindings/pinctrl/
H A Dpinctrl-st.txt3 Each multi-function pin is controlled, driven and routed through the
5 and multiple alternate functions(ALT1 - ALTx) that directly connect
14 GPIO bank can have one of the two possible types of interrupt-wirings.
17 reduces number of overall interrupts numbers required. All these banks belong to
20 | |----> [gpio-bank (n) ]
21 | |----> [gpio-bank (n + 1)]
22 [irqN]-- | irq-mux |----> [gpio-bank (n + 2)]
23 | |----> [gpio-bank (... )]
24 |_________|----> [gpio-bank (n + 7)]
26 Second type has a dedicated interrupt per gpio bank.
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H A Dmicrochip,sparx5-sgpio.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/microchip,sparx5-sgpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lars Povlsen <lars.povlsen@microchip.com>
14 the number of available GPIOs with a minimum number of additional
21 pattern: "^gpio@[0-9a-f]+$"
25 - microchip,sparx5-sgpio
26 - mscc,ocelot-sgpio
27 - mscc,luton-sgpio
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/openbmc/linux/drivers/gpio/
H A Dgpio-zynq.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright (C) 2009 - 2014 Xilinx, Inc.
20 #define DRIVER_NAME "zynq-gpio"
46 ZYNQ##str##_GPIO_BANK0_NGPIO - 1)
49 ZYNQ##str##_GPIO_BANK1_NGPIO - 1)
52 ZYNQ##str##_GPIO_BANK2_NGPIO - 1)
55 ZYNQ##str##_GPIO_BANK3_NGPIO - 1)
58 ZYNQ##str##_GPIO_BANK4_NGPIO - 1)
61 ZYNQ##str##_GPIO_BANK5_NGPIO - 1)
64 /* LSW Mask & Data -WO */
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/openbmc/linux/drivers/pinctrl/
H A Dpinctrl-equilibrium.h1 /* SPDX-License-Identifier: GPL-2.0 */
18 #define DRV_CUR_PINS 16 /* Drive Current pin number per register */
74 * @nr_groups: number of groups included in @groups.
83 * struct eqbr_pin_bank: represent a pin bank.
84 * @membase: base address of the pin bank register.
85 * @id: bank id, to idenify the unique bank.
86 * @pin_base: starting pin number of the pin bank.
87 * @nr_pins: number of the pins of the pin bank.
88 * @aval_pinmap: available pin bitmap of the pin bank.
104 * @bank: pointer to corresponding pin bank.
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H A Dpinctrl-rockchip.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (c) 2020-2021 Rockchip Electronics Co. Ltd.
8 * With some ideas taken from pinctrl-samsung:
14 * and pinctrl-at91:
15 * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
242 * @offset: if initialized to -1 it will be autocalculated, by specifying
275 * @offset: if initialized to -1 it will be autocalculated, by specifying
288 * @dev: the pinctrl device bind to the bank
289 * @reg_base: register base of the gpio bank
291 * @clk: clock of the gpio bank
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/openbmc/linux/drivers/thermal/mediatek/
H A Dauxadc_thermal.c1 // SPDX-License-Identifier: GPL-2.0-only
15 #include <linux/nvmem-consumer.h>
103 /* The total number of temperature sensors in the MT8173 */
106 /* The number of banks in the MT8173 */
109 /* The number of sensing points per bank */
112 /* The number of controller in the MT8173 */
119 #define MT8173_TEMP_MIN -20000
195 /* The total number of temperature sensors in the MT2701 */
198 /* The number of sensing points per bank */
201 /* The number of controller in the MT2701 */
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/openbmc/linux/Documentation/hwmon/
H A Dabituguru-datasheet.rst14 Olle Sandberg <ollebull@gmail.com>, 2005-05-25
27 Hans de Goede <j.w.r.degoede@hhs.nl>, 28-01-2006
33 As far as known the uGuru is always placed at and using the (ISA) I/O-ports
34 0xE0 and 0xE4, so we don't have to scan any port-range, just check what the two
35 ports are holding for detection. We will refer to 0xE0 as CMD (command-port)
39 present. We have to check for two different values at data-port, because
41 later on attached again data-port will hold 0x08, more about this later.
57 ----------
59 The uGuru has a number of different addressing levels. The first addressing
60 level we will call banks. A bank holds data for one or more sensors. The data
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/openbmc/linux/Documentation/devicetree/bindings/gpio/
H A Dbrcm,brcmstb-gpio.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpio/brcm,brcmstb-gpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 The controller's registers are organized as sets of eight 32-bit
11 registers with each set controlling a bank of up to 32 pins. A single
15 - Doug Berger <opendmb@gmail.com>
16 - Florian Fainelli <f.fainelli@gmail.com>
21 - enum:
22 - brcm,bcm7445-gpio
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/openbmc/linux/drivers/mtd/nand/raw/
H A Ddenali.h1 /* SPDX-License-Identifier: GPL-2.0 */
4 * Copyright (c) 2009 - 2010, Intel Corporation and its suppliers.
18 #define DEVICE_RESET__BANK(bank) BIT(bank) argument
36 #define RB_PIN_ENABLED__BANK(bank) BIT(bank) argument
208 #define INTR_STATUS(bank) (0x410 + (bank) * 0x50) argument
209 #define INTR_EN(bank) (0x420 + (bank) * 0x50) argument
230 #define PAGE_CNT(bank) (0x430 + (bank) * 0x50) argument
231 #define ERR_PAGE_ADDR(bank) (0x440 + (bank) * 0x50) argument
232 #define ERR_BLOCK_ADDR(bank) (0x450 + (bank) * 0x50) argument
254 #define ECC_COR_INFO(bank) (0x650 + (bank) / 2 * 0x10) argument
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/openbmc/linux/Documentation/devicetree/bindings/mtd/
H A Dfsmc-nand.txt5 - compatible : "st,spear600-fsmc-nand", "stericsson,fsmc-nand"
6 - reg : Address range of the mtd chip
7 - reg-names: Should contain the reg names "fsmc_regs", "nand_data", "nand_addr" and "nand_cmd"
10 - bank-width : Width (in bytes) of the device. If not present, the width
12 - nand-skip-bbtscan: Indicates the BBT scanning should be skipped
13 - timings: array of 6 bytes for NAND timings. The meanings of these bytes
15 byte 0 TCLR : CLE to RE delay in number of AHB clock cycles, only 4 bits
19 byte 2 THIZ : number of HCLK clock cycles during which the data bus is
20 kept in Hi-Z (tristate) after the start of a write access.
23 byte 3 THOLD : number of HCLK clock cycles to hold the address (and data
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/openbmc/linux/drivers/mtd/devices/
H A Dspear_smi.c157 * struct spear_smi - Structure for SMI Device
165 * @cmd_complete: queue to wait for command completion of NOR-flash.
166 * @num_flashes: number of flashes actually present on board.
167 * @flash: separate structure for each Serial NOR-flash attached to SMI.
182 * struct spear_snor_flash - Structure for Serial NOR Flash
184 * @bank: Bank number(0, 1, 2, 3) for each NOR-flash.
185 * @dev_id: Device ID of NOR-flash.
187 * @mtd: MTD info for each NOR-flash.
188 * @num_parts: Total number of partition in each bank of NOR-flash.
189 * @parts: Partition info for each bank of NOR-flash.
[all …]
/openbmc/u-boot/drivers/pinctrl/rockchip/
H A Dpinctrl-rockchip.h1 /* SPDX-License-Identifier: GPL-2.0+ */
44 * @offset: if initialized to -1 it will be autocalculated, by specifying
82 * @offset: if initialized to -1 it will be autocalculated, by specifying
95 * @pin_base: first pin number
96 * @nr_pins: number of pins in this bank
97 * @name: name of the bank
98 * @bank_num: number of the bank, to account for holes
99 * @iomux: array describing the 4 iomux sources of the bank
100 * @drv: array describing the 4 drive strength sources of the bank
101 * @pull_type: array describing the 4 pull type sources of the bank
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/openbmc/linux/Documentation/devicetree/bindings/soc/fsl/cpm_qe/
H A Dgpio.txt1 Every GPIO controller node must have #gpio-cells property defined,
2 this information will be used to translate gpio-specifiers.
10 - compatible : "fsl,cpm1-pario-bank-a", "fsl,cpm1-pario-bank-b",
11 "fsl,cpm1-pario-bank-c", "fsl,cpm1-pario-bank-d",
12 "fsl,cpm1-pario-bank-e", "fsl,cpm2-pario-bank"
13 - #gpio-cells : Should be two. The first cell is the pin number and the
15 - gpio-controller : Marks the port as GPIO controller.
17 - fsl,cpm1-gpio-irq-mask : For banks having interrupt capability (like port C
20 - interrupts : This property provides the list of interrupt for each GPIO having
21 one as described by the fsl,cpm1-gpio-irq-mask property. There should be as
[all …]
/openbmc/linux/drivers/memory/
H A Djz4780-nemc.c1 // SPDX-License-Identifier: GPL-2.0-only
6 * Author: Alex Smith <alex@alex-smith.me.uk>
20 #include <linux/jz4780-nemc.h>
22 #define NEMC_SMCRn(n) (0x14 + (((n) - 1) * 4))
42 #define NEMC_NFCSR_NFEn(n) BIT(((n) - 1) << 1)
43 #define NEMC_NFCSR_NFCEn(n) BIT((((n) - 1) << 1) + 1)
44 #define NEMC_NFCSR_TNFEn(n) BIT(16 + (n) - 1)
61 * jz4780_nemc_num_banks() - count the number of banks referenced by a device
64 * Return: The number of unique NEMC banks referred to by the specified NEMC
65 * child device. Unique here means that a device that references the same bank
[all …]
/openbmc/linux/arch/x86/include/uapi/asm/
H A Dmce.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
14 __u64 status; /* Bank's MCi_STATUS MSR */
15 __u64 misc; /* Bank's MCi_MISC MSR */
16 __u64 addr; /* Bank's MCi_ADDR MSR */
27 __u8 bank; /* Machine check bank reporting the error */ member
28 __u8 cpu; /* CPU number; obsoleted by extcpu */
30 __u32 extcpu; /* Linux CPU number that detected the error */
36 __u64 ppin; /* Protected Processor Inventory Number */

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