pinctrl/samsung/pinctrl-samsung.h

1 /* SPDX-License-Identifier: GPL-2.0+ */
3  * pin-controller/pin-mux/pin-config/gpio-driver for Samsung's SoC's.
25  * enum pincfg_type - possible pin configuration types supported.
46  * packed together into a 16-bits. The upper 8-bits represent the configuration
47  * type and the lower 8-bits hold the value of the configuration type.
65  * enum eint_type - possible external interrupt types.
66  * @EINT_TYPE_NONE: bank does not support external interrupts
67  * @EINT_TYPE_GPIO: bank supportes external gpio interrupts
68  * @EINT_TYPE_WKUP: bank supportes external wakeup interrupts
69  * @EINT_TYPE_WKUP_MUX: bank supports multiplexed external wakeup interrupts
72  * in a pin bank can support external gpio interrupts or external wakeup
85 /* maximum length of a pin in pin descriptor (example: "gpa0-0") */
106  * struct samsung_pin_bank_type: pin bank type description
116  * struct samsung_pin_bank_data: represent a controller pin-bank (init data).
117  * @type: type of the bank (register offsets and bitfield widths)
118  * @pctl_offset: starting offset of the pin-bank registers.
119  * @pctl_res_idx: index of base address for pin-bank registers.
120  * @nr_pins: number of pins included in this bank.
122  * @eint_type: type of the external interrupt supported by the bank.
124  * @eint_offset: SoC-specific EINT register or interrupt offset of bank.
125  * @name: name to be prefixed for each pin in this pin bank.
140  * struct samsung_pin_bank: represent a controller pin-bank.
141  * @type: type of the bank (register offsets and bitfield widths)
142  * @pctl_base: base address of the pin-bank registers
143  * @pctl_offset: starting offset of the pin-bank registers.
144  * @nr_pins: number of pins included in this bank.
145  * @eint_base: base address of the pin-bank EINT registers.
147  * @eint_type: type of the external interrupt supported by the bank.
149  * @eint_offset: SoC-specific EINT register or interrupt offset of bank.
150  * @name: name to be prefixed for each pin in this pin bank.
151  * @pin_base: starting pin number of the bank.
152  * @soc_priv: per-bank private data for SoC-specific code.
153  * @of_node: OF node of the bank.
155  * @irq_domain: IRQ domain of the bank.
156  * @gpio_chip: GPIO chip of the bank.
157  * @grange: linux gpio pin range supported by this bank.
159  * @slock: spinlock protecting bank registers
188  * struct samsung_retention_data: runtime pin-bank retention control data.
190  * @nr_regs: number of registers in @regs array.
192  * @refcnt: atomic counter if retention control affects more than one bank.
208  * struct samsung_retention_data: represent a pin-bank retention control data.
210  * @nr_regs: number of registers in @regs array.
212  * @refcnt: atomic counter if retention control affects more than one bank.
227  * @nr_banks: number of pin banks.
228  * @nr_ext_resources: number of the extra base address for pin banks.
258  *             to each bank samsung_pin_bank->pctl_base and used on legacy
262  * @irq: interrpt number used by the controller to notify gpio interrupts.
267  * @nr_groups: number of such pin groups.
269  * @nr_function: number of such pin functions.
270  * @pin_base: starting system wide pin number.
271  * @nr_pins: number of pins supported by the controller.
317  * @num_pins: number of pins included in this group.
318  * @func: the function number to be programmed when selected.
331  * @num_groups: number of groups included in @groups.