Home
last modified time | relevance | path

Searched +full:64 +full:- (Results 1 – 25 of 1166) sorted by relevance

12345678910>>...47

/openbmc/qemu/tests/qemu-iotests/tests/
H A Dimage-fleecing.out3 --- Setting up images ---
7 --- Launching VM ---
11 --- Setting up Fleecing Graph ---
16 --- Setting up NBD Export ---
21 --- Sanity Check ---
23 read -P0x5d 0 64k
24 read -P0xd5 1M 64k
25 read -P0xdc 32M 64k
26 read -P0xcd 0x3ff0000 64k
27 read -P0 0x00f8000 32k
[all …]
/openbmc/u-boot/drivers/mtd/spi/
H A Dspi-nor-ids.c1 // SPDX-License-Identifier: GPL-2.0+
6 * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
67 /* Atmel -- some are (confusingly) marketed as "DataFlash" */
68 { INFO("at26df321", 0x1f4700, 0, 64 * 1024, 64, SECT_4K) },
69 { INFO("at25df321a", 0x1f4701, 0, 64 * 1024, 64, SECT_4K) },
71 { INFO("at45db011d", 0x1f2200, 0, 64 * 1024, 4, SECT_4K) },
72 { INFO("at45db021d", 0x1f2300, 0, 64 * 1024, 8, SECT_4K) },
73 { INFO("at45db041d", 0x1f2400, 0, 64 * 1024, 8, SECT_4K) },
74 { INFO("at45db081d", 0x1f2500, 0, 64 * 1024, 16, SECT_4K) },
75 { INFO("at45db161d", 0x1f2600, 0, 64 * 1024, 32, SECT_4K) },
[all …]
/openbmc/linux/fs/btrfs/
H A Daccessors.h1 /* SPDX-License-Identifier: GPL-2.0 */
61 DECLARE_BTRFS_SETGET_BITS(64)
92 const type *p = page_address(eb->pages[0]) + \
93 offset_in_page(eb->start); \
94 return get_unaligned_le##bits(&p->member); \
99 type *p = page_address(eb->pages[0]) + offset_in_page(eb->start); \
100 put_unaligned_le##bits(val, &p->member); \
106 return get_unaligned_le##bits(&s->member); \
110 put_unaligned_le##bits(val, &s->member); \
124 WARN_ON(!IS_ALIGNED(val, eb->fs_info->sectorsize)); in btrfs_set_device_total_bytes()
[all …]
/openbmc/qemu/tests/tcg/mips/user/ase/msa/
H A Dtest_msa_compile_64r6el.sh4 # ---------
6 /opt/img/bin/mips-img-linux-gnu-gcc bit-count/test_msa_nloc_b.c \
7 -EL -static -mabi=64 -march=mips64r6 -mmsa -o /tmp/test_msa_nloc_b_64r6el
8 /opt/img/bin/mips-img-linux-gnu-gcc bit-count/test_msa_nloc_h.c \
9 -EL -static -mabi=64 -march=mips64r6 -mmsa -o /tmp/test_msa_nloc_h_64r6el
10 /opt/img/bin/mips-img-linux-gnu-gcc bit-count/test_msa_nloc_w.c \
11 -EL -static -mabi=64 -march=mips64r6 -mmsa -o /tmp/test_msa_nloc_w_64r6el
12 /opt/img/bin/mips-img-linux-gnu-gcc bit-count/test_msa_nloc_d.c \
13 -EL -static -mabi=64 -march=mips64r6 -mmsa -o /tmp/test_msa_nloc_d_64r6el
14 /opt/img/bin/mips-img-linux-gnu-gcc bit-count/test_msa_nlzc_b.c \
[all …]
H A Dtest_msa_compile_64r6eb.sh4 # ---------
6 /opt/img/bin/mips-img-linux-gnu-gcc bit-count/test_msa_nloc_b.c \
7 -EB -static -mabi=64 -march=mips64r6 -mmsa -o /tmp/test_msa_nloc_b_64r6eb
8 /opt/img/bin/mips-img-linux-gnu-gcc bit-count/test_msa_nloc_h.c \
9 -EB -static -mabi=64 -march=mips64r6 -mmsa -o /tmp/test_msa_nloc_h_64r6eb
10 /opt/img/bin/mips-img-linux-gnu-gcc bit-count/test_msa_nloc_w.c \
11 -EB -static -mabi=64 -march=mips64r6 -mmsa -o /tmp/test_msa_nloc_w_64r6eb
12 /opt/img/bin/mips-img-linux-gnu-gcc bit-count/test_msa_nloc_d.c \
13 -EB -static -mabi=64 -march=mips64r6 -mmsa -o /tmp/test_msa_nloc_d_64r6eb
14 /opt/img/bin/mips-img-linux-gnu-gcc bit-count/test_msa_nlzc_b.c \
[all …]
/openbmc/openbmc/poky/meta/conf/machine/include/x86/
H A Dtune-x86-64-v3.inc1 # Settings for the GCC(1) cpu-type "x86-64-v3":
5 # See https://www.phoronix.com/news/GCC-11-x86-64-Feature-Levels for details.
9 DEFAULTTUNE ?= "x86-64-v3"
12 require conf/machine/include/x86/tune-corei7.inc
15 TUNEVALID[x86-64-v3] = "Enable x86-64-v3 specific processor optimizations"
16 TUNE_CCARGS .= "${@bb.utils.contains('TUNE_FEATURES', 'x86-64-v3', ' -march=x86-64-v3', '', d)}"
19 AVAILTUNES += "x86-64-v3"
20 TUNE_FEATURES:tune-x86-64-v3 = "${TUNE_FEATURES:tune-x86-64} x86-64-v3"
21 BASE_LIB:tune-x86-64-v3 = "lib64"
22 TUNE_PKGARCH:tune-x86-64-v3 = "x86-64-v3"
[all …]
H A Dtune-corei7.inc1 # Settings for the GCC(1) cpu-type "nehalem":
3 # Intel Nehalem CPU with 64-bit extensions, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1,
9 DEFAULTTUNE ?= "corei7-64"
12 require conf/machine/include/x86/tune-core2.inc
16 ….= "${@bb.utils.contains('TUNE_FEATURES', 'corei7', ' -march=nehalem -mtune=generic -mfpmath=sse -…
19 AVAILTUNES += "corei7-32"
20 TUNE_FEATURES:tune-corei7-32 = "${TUNE_FEATURES:tune-x86} corei7"
21 BASE_LIB:tune-corei7-32 = "lib"
22 TUNE_PKGARCH:tune-corei7-32 = "corei7-32"
23 PACKAGE_EXTRA_ARCHS:tune-corei7-32 = "${PACKAGE_EXTRA_ARCHS:tune-core2-32} corei7-32"
[all …]
/openbmc/qemu/gdb-xml/
H A Daarch64-core.xml2 <!-- Copyright (C) 2009-2012 Free Software Foundation, Inc.
7 notice and this notice are preserved. -->
9 <!DOCTYPE feature SYSTEM "gdb-target.dtd">
11 <reg name="x0" bitsize="64"/>
12 <reg name="x1" bitsize="64"/>
13 <reg name="x2" bitsize="64"/>
14 <reg name="x3" bitsize="64"/>
15 <reg name="x4" bitsize="64"/>
16 <reg name="x5" bitsize="64"/>
17 <reg name="x6" bitsize="64"/>
[all …]
H A Dpower64-core.xml2 <!-- Copyright (C) 2007, 2008 Free Software Foundation, Inc.
6 notice and this notice are preserved. -->
8 <!DOCTYPE feature SYSTEM "gdb-target.dtd">
10 <reg name="r0" bitsize="64" type="uint64"/>
11 <reg name="r1" bitsize="64" type="uint64"/>
12 <reg name="r2" bitsize="64" type="uint64"/>
13 <reg name="r3" bitsize="64" type="uint64"/>
14 <reg name="r4" bitsize="64" type="uint64"/>
15 <reg name="r5" bitsize="64" type="uint64"/>
16 <reg name="r6" bitsize="64" type="uint64"/>
[all …]
H A Dpower-vsx.xml2 <!-- Copyright (C) 2008-2015 Free Software Foundation, Inc.
6 notice and this notice are preserved. -->
8 <!-- POWER7 VSX registers that do not overlap existing FP and VMX
9 registers. -->
10 <!DOCTYPE feature SYSTEM "gdb-target.dtd">
12 <reg name="vs0h" bitsize="64" type="uint64"/>
13 <reg name="vs1h" bitsize="64" type="uint64"/>
14 <reg name="vs2h" bitsize="64" type="uint64"/>
15 <reg name="vs3h" bitsize="64" type="uint64"/>
16 <reg name="vs4h" bitsize="64" type="uint64"/>
[all …]
H A Driscv-64bit-cpu.xml2 <!-- Copyright (C) 2018-2019 Free Software Foundation, Inc.
6 notice and this notice are preserved. -->
8 <!DOCTYPE feature SYSTEM "gdb-target.dtd">
10 <reg name="zero" bitsize="64" type="int"/>
11 <reg name="ra" bitsize="64" type="code_ptr"/>
12 <reg name="sp" bitsize="64" type="data_ptr"/>
13 <reg name="gp" bitsize="64" type="data_ptr"/>
14 <reg name="tp" bitsize="64" type="data_ptr"/>
15 <reg name="t0" bitsize="64" type="int"/>
16 <reg name="t1" bitsize="64" type="int"/>
[all …]
H A Driscv-64bit-fpu.xml2 <!-- Copyright (C) 2018-2019 Free Software Foundation, Inc.
6 notice and this notice are preserved. -->
8 <!DOCTYPE feature SYSTEM "gdb-target.dtd">
16 <reg name="ft0" bitsize="64" type="riscv_double"/>
17 <reg name="ft1" bitsize="64" type="riscv_double"/>
18 <reg name="ft2" bitsize="64" type="riscv_double"/>
19 <reg name="ft3" bitsize="64" type="riscv_double"/>
20 <reg name="ft4" bitsize="64" type="riscv_double"/>
21 <reg name="ft5" bitsize="64" type="riscv_double"/>
22 <reg name="ft6" bitsize="64" type="riscv_double"/>
[all …]
H A Dloongarch-base64.xml2 <!-- Copyright (C) 2022 Free Software Foundation, Inc.
6 notice and this notice are preserved. -->
8 <!DOCTYPE feature SYSTEM "gdb-target.dtd">
10 <reg name="r0" bitsize="64" type="uint64" group="general"/>
11 <reg name="r1" bitsize="64" type="code_ptr" group="general"/>
12 <reg name="r2" bitsize="64" type="data_ptr" group="general"/>
13 <reg name="r3" bitsize="64" type="data_ptr" group="general"/>
14 <reg name="r4" bitsize="64" type="uint64" group="general"/>
15 <reg name="r5" bitsize="64" type="uint64" group="general"/>
16 <reg name="r6" bitsize="64" type="uint64" group="general"/>
[all …]
H A Darm-vfp3.xml2 <!-- Copyright (C) 2008 Free Software Foundation, Inc.
6 notice and this notice are preserved. -->
7 <!DOCTYPE feature SYSTEM "gdb-target.dtd">
9 <reg name="d0" bitsize="64" type="float"/>
10 <reg name="d1" bitsize="64" type="float"/>
11 <reg name="d2" bitsize="64" type="float"/>
12 <reg name="d3" bitsize="64" type="float"/>
13 <reg name="d4" bitsize="64" type="float"/>
14 <reg name="d5" bitsize="64" type="float"/>
15 <reg name="d6" bitsize="64" type="float"/>
[all …]
H A Dpower-fpu.xml2 <!-- Copyright (C) 2007, 2008 Free Software Foundation, Inc.
6 notice and this notice are preserved. -->
8 <!DOCTYPE feature SYSTEM "gdb-target.dtd">
10 <reg name="f0" bitsize="64" type="ieee_double" regnum="71"/>
11 <reg name="f1" bitsize="64" type="ieee_double"/>
12 <reg name="f2" bitsize="64" type="ieee_double"/>
13 <reg name="f3" bitsize="64" type="ieee_double"/>
14 <reg name="f4" bitsize="64" type="ieee_double"/>
15 <reg name="f5" bitsize="64" type="ieee_double"/>
16 <reg name="f6" bitsize="64" type="ieee_double"/>
[all …]
H A Dloongarch-fpu.xml2 <!-- Copyright (C) 2021 Free Software Foundation, Inc.
6 notice and this notice are preserved. -->
8 <!DOCTYPE feature SYSTEM "gdb-target.dtd">
16 <reg name="f0" bitsize="64" type="fputype" group="float"/>
17 <reg name="f1" bitsize="64" type="fputype" group="float"/>
18 <reg name="f2" bitsize="64" type="fputype" group="float"/>
19 <reg name="f3" bitsize="64" type="fputype" group="float"/>
20 <reg name="f4" bitsize="64" type="fputype" group="float"/>
21 <reg name="f5" bitsize="64" type="fputype" group="float"/>
22 <reg name="f6" bitsize="64" type="fputype" group="float"/>
[all …]
/openbmc/linux/arch/arm/boot/dts/nvidia/
H A Dtegra124-peripherals-opp.dtsi1 // SPDX-License-Identifier: GPL-2.0
4 emc_icc_dvfs_opp_table: opp-table-emc {
5 compatible = "operating-points-v2";
7 opp-12750000-800 {
8 opp-microvolt = <800000 800000 1150000>;
9 opp-hz = /bits/ 64 <12750000>;
10 opp-supported-hw = <0x0003>;
13 opp-12750000-950 {
14 opp-microvolt = <950000 950000 1150000>;
15 opp-hz = /bits/ 64 <12750000>;
[all …]
H A Dtegra30-peripherals-opp.dtsi1 // SPDX-License-Identifier: GPL-2.0
4 core_opp_table: opp-table-core {
5 compatible = "operating-points-v2";
6 opp-shared;
8 core_opp_950: opp-950000 {
9 opp-microvolt = <950000 950000 1350000>;
10 opp-level = <950000>;
13 core_opp_1000: opp-1000000 {
14 opp-microvolt = <1000000 1000000 1350000>;
15 opp-level = <1000000>;
[all …]
H A Dtegra20-peripherals-opp.dtsi1 // SPDX-License-Identifier: GPL-2.0
4 core_opp_table: opp-table-core {
5 compatible = "operating-points-v2";
6 opp-shared;
8 core_opp_950: opp-950000 {
9 opp-microvolt = <950000 950000 1300000>;
10 opp-level = <950000>;
13 core_opp_1000: opp-1000000 {
14 opp-microvolt = <1000000 1000000 1300000>;
15 opp-level = <1000000>;
[all …]
/openbmc/linux/tools/testing/selftests/drivers/net/mlxsw/
H A Dfib_offload.sh2 # SPDX-License-Identifier: GPL-2.0
43 __addr_add_del $spine_p1 add 2001:db8:1::1/64
44 __addr_add_del $spine_p2 add 2001:db8:2::1/64
49 __addr_add_del $spine_p2 del 2001:db8:2::1/64
50 __addr_add_del $spine_p1 del 2001:db8:1::1/64
65 num=$(ip -6 route show match ${pfx} | grep "offload" | wc -l)
67 if [ $num -eq $expected_num ]; then
79 ip -6 route add 2001:db8:3::/64 dev $spine_p1 metric 100
80 ipv6_offload_check "2001:db8:3::/64 dev $spine_p1 metric 100" 1
85 ip -6 route append 2001:db8:3::/64 dev $spine_p1 metric 200
[all …]
/openbmc/linux/arch/arm64/boot/dts/nvidia/
H A Dtegra132-peripherals-opp.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 emc_icc_dvfs_opp_table: opp-table-dvfs0 {
6 compatible = "operating-points-v2";
8 opp-12750000-800 {
9 opp-microvolt = <800000 800000 1150000>;
10 opp-hz = /bits/ 64 <12750000>;
11 opp-supported-hw = <0x0003>;
14 opp-12750000-950 {
15 opp-microvolt = <950000 950000 1150000>;
16 opp-hz = /bits/ 64 <12750000>;
[all …]
/openbmc/linux/arch/loongarch/lib/
H A Dcsum.c1 // SPDX-License-Identifier: GPL-2.0-only
2 // Copyright (C) 2019-2020 Arm Ltd.
5 #include <linux/kasan-checks.h>
19 * We over-read the buffer and this makes KASAN unhappy. Instead, disable
35 * should absolutely not be pointing to anything read-sensitive. We do, in do_csum()
38 * compensate with an explicit check up-front. in do_csum()
41 ptr = (u64 *)(buff - offset); in do_csum()
42 len = len + offset - 8; in do_csum()
59 while (unlikely(len > 64)) { in do_csum()
67 len -= 64; in do_csum()
[all …]
/openbmc/linux/arch/arm64/lib/
H A Dcsum.c1 // SPDX-License-Identifier: GPL-2.0-only
2 // Copyright (C) 2019-2020 Arm Ltd.
5 #include <linux/kasan-checks.h>
10 /* Looks dumb, but generates nice-ish code */
14 return tmp + (tmp >> 64); in accumulate()
18 * We over-read the buffer and this makes KASAN unhappy. Instead, disable
34 * should absolutely not be pointing to anything read-sensitive. We do, in do_csum()
37 * compensate with an explicit check up-front. in do_csum()
40 ptr = (u64 *)(buff - offset); in do_csum()
41 len = len + offset - 8; in do_csum()
[all …]
/openbmc/linux/arch/riscv/include/asm/
H A Dgdb_xml.h1 /* SPDX-License-Identifier: GPL-2.0-only */
6 const char riscv_gdb_stub_feature[64] =
13 "qXfer:features:read:riscv-64bit-cpu.xml";
17 "<!DOCTYPE target SYSTEM \"gdb-target.dtd\">"
19 "<xi:include href=\"riscv-64bit-cpu.xml\"/>"
24 "<!DOCTYPE feature SYSTEM \"gdb-target.dtd\">"
26 "<reg name=\""DBG_REG_ZERO"\" bitsize=\"64\" type=\"int\" regnum=\"0\"/>"
27 "<reg name=\""DBG_REG_RA"\" bitsize=\"64\" type=\"code_ptr\"/>"
28 "<reg name=\""DBG_REG_SP"\" bitsize=\"64\" type=\"data_ptr\"/>"
29 "<reg name=\""DBG_REG_GP"\" bitsize=\"64\" type=\"data_ptr\"/>"
[all …]
/openbmc/qemu/linux-user/sparc/
H A Dsyscall.tbl1 # SPDX-License-Identifier: GPL-2.0-only WITH Linux-syscall-note
8 # The <abi> can be common, 64, or 32 for this file.
12 1 64 exit sparc_exit
23 11 64 execv sys_nis_syscall
26 13 64 chown sys_chown
30 16 64 lchown sys_lchown
38 23 64 setuid sys_setuid
40 24 64 getuid sys_getuid
46 29 64 pause sys_nis_syscall
48 30 64 utime sys_utime
[all …]

12345678910>>...47