1778572d7SVignesh R // SPDX-License-Identifier: GPL-2.0+ 2778572d7SVignesh R /* 3778572d7SVignesh R * 4778572d7SVignesh R * Copyright (C) 2013 Jagannadha Sutradharudu Teki, Xilinx Inc. 5778572d7SVignesh R * Copyright (C) 2016 Jagan Teki <jagan@openedev.com> 6778572d7SVignesh R * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ 7778572d7SVignesh R */ 8778572d7SVignesh R 9778572d7SVignesh R #include <common.h> 10778572d7SVignesh R #include <spi.h> 11778572d7SVignesh R #include <spi_flash.h> 12778572d7SVignesh R 13778572d7SVignesh R #include "sf_internal.h" 14778572d7SVignesh R 15778572d7SVignesh R /* Exclude chip names for SPL to save space */ 16778572d7SVignesh R #if !CONFIG_IS_ENABLED(SPI_FLASH_TINY) 17778572d7SVignesh R #define INFO_NAME(_name) .name = _name, 18778572d7SVignesh R #else 19778572d7SVignesh R #define INFO_NAME(_name) 20778572d7SVignesh R #endif 21778572d7SVignesh R 22778572d7SVignesh R /* Used when the "_ext_id" is two bytes at most */ 23778572d7SVignesh R #define INFO(_name, _jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \ 24778572d7SVignesh R INFO_NAME(_name) \ 25778572d7SVignesh R .id = { \ 26778572d7SVignesh R ((_jedec_id) >> 16) & 0xff, \ 27778572d7SVignesh R ((_jedec_id) >> 8) & 0xff, \ 28778572d7SVignesh R (_jedec_id) & 0xff, \ 29778572d7SVignesh R ((_ext_id) >> 8) & 0xff, \ 30778572d7SVignesh R (_ext_id) & 0xff, \ 31778572d7SVignesh R }, \ 32778572d7SVignesh R .id_len = (!(_jedec_id) ? 0 : (3 + ((_ext_id) ? 2 : 0))), \ 33778572d7SVignesh R .sector_size = (_sector_size), \ 34778572d7SVignesh R .n_sectors = (_n_sectors), \ 35778572d7SVignesh R .page_size = 256, \ 36778572d7SVignesh R .flags = (_flags), 37778572d7SVignesh R 38778572d7SVignesh R #define INFO6(_name, _jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \ 39778572d7SVignesh R INFO_NAME(_name) \ 40778572d7SVignesh R .id = { \ 41778572d7SVignesh R ((_jedec_id) >> 16) & 0xff, \ 42778572d7SVignesh R ((_jedec_id) >> 8) & 0xff, \ 43778572d7SVignesh R (_jedec_id) & 0xff, \ 44778572d7SVignesh R ((_ext_id) >> 16) & 0xff, \ 45778572d7SVignesh R ((_ext_id) >> 8) & 0xff, \ 46778572d7SVignesh R (_ext_id) & 0xff, \ 47778572d7SVignesh R }, \ 48778572d7SVignesh R .id_len = 6, \ 49778572d7SVignesh R .sector_size = (_sector_size), \ 50778572d7SVignesh R .n_sectors = (_n_sectors), \ 51778572d7SVignesh R .page_size = 256, \ 52778572d7SVignesh R .flags = (_flags), 53778572d7SVignesh R 54778572d7SVignesh R /* NOTE: double check command sets and memory organization when you add 55778572d7SVignesh R * more nor chips. This current list focusses on newer chips, which 56778572d7SVignesh R * have been converging on command sets which including JEDEC ID. 57778572d7SVignesh R * 58778572d7SVignesh R * All newly added entries should describe *hardware* and should use SECT_4K 59778572d7SVignesh R * (or SECT_4K_PMC) if hardware supports erasing 4 KiB sectors. For usage 60778572d7SVignesh R * scenarios excluding small sectors there is config option that can be 61778572d7SVignesh R * disabled: CONFIG_MTD_SPI_NOR_USE_4K_SECTORS. 62778572d7SVignesh R * For historical (and compatibility) reasons (before we got above config) some 63778572d7SVignesh R * old entries may be missing 4K flag. 64778572d7SVignesh R */ 65778572d7SVignesh R const struct flash_info spi_nor_ids[] = { 66778572d7SVignesh R #ifdef CONFIG_SPI_FLASH_ATMEL /* ATMEL */ 67778572d7SVignesh R /* Atmel -- some are (confusingly) marketed as "DataFlash" */ 68778572d7SVignesh R { INFO("at26df321", 0x1f4700, 0, 64 * 1024, 64, SECT_4K) }, 69778572d7SVignesh R { INFO("at25df321a", 0x1f4701, 0, 64 * 1024, 64, SECT_4K) }, 70778572d7SVignesh R 71778572d7SVignesh R { INFO("at45db011d", 0x1f2200, 0, 64 * 1024, 4, SECT_4K) }, 72778572d7SVignesh R { INFO("at45db021d", 0x1f2300, 0, 64 * 1024, 8, SECT_4K) }, 73778572d7SVignesh R { INFO("at45db041d", 0x1f2400, 0, 64 * 1024, 8, SECT_4K) }, 74778572d7SVignesh R { INFO("at45db081d", 0x1f2500, 0, 64 * 1024, 16, SECT_4K) }, 75778572d7SVignesh R { INFO("at45db161d", 0x1f2600, 0, 64 * 1024, 32, SECT_4K) }, 76778572d7SVignesh R { INFO("at45db321d", 0x1f2700, 0, 64 * 1024, 64, SECT_4K) }, 77778572d7SVignesh R { INFO("at45db641d", 0x1f2800, 0, 64 * 1024, 128, SECT_4K) }, 78778572d7SVignesh R { INFO("at26df081a", 0x1f4501, 0, 64 * 1024, 16, SECT_4K) }, 79778572d7SVignesh R #endif 80778572d7SVignesh R #ifdef CONFIG_SPI_FLASH_EON /* EON */ 81778572d7SVignesh R /* EON -- en25xxx */ 82778572d7SVignesh R { INFO("en25q32b", 0x1c3016, 0, 64 * 1024, 64, 0) }, 83778572d7SVignesh R { INFO("en25q64", 0x1c3017, 0, 64 * 1024, 128, SECT_4K) }, 84778572d7SVignesh R { INFO("en25qh128", 0x1c7018, 0, 64 * 1024, 256, 0) }, 85778572d7SVignesh R { INFO("en25s64", 0x1c3817, 0, 64 * 1024, 128, SECT_4K) }, 86778572d7SVignesh R #endif 87778572d7SVignesh R #ifdef CONFIG_SPI_FLASH_GIGADEVICE /* GIGADEVICE */ 88778572d7SVignesh R /* GigaDevice */ 89778572d7SVignesh R { 90778572d7SVignesh R INFO("gd25q16", 0xc84015, 0, 64 * 1024, 32, 91778572d7SVignesh R SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 92778572d7SVignesh R SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) 93778572d7SVignesh R }, 94778572d7SVignesh R { 95778572d7SVignesh R INFO("gd25q32", 0xc84016, 0, 64 * 1024, 64, 96778572d7SVignesh R SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 97778572d7SVignesh R SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) 98778572d7SVignesh R }, 99778572d7SVignesh R { 100778572d7SVignesh R INFO("gd25lq32", 0xc86016, 0, 64 * 1024, 64, 101778572d7SVignesh R SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 102778572d7SVignesh R SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) 103778572d7SVignesh R }, 104778572d7SVignesh R { 105778572d7SVignesh R INFO("gd25q64", 0xc84017, 0, 64 * 1024, 128, 106778572d7SVignesh R SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 107778572d7SVignesh R SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) 108778572d7SVignesh R }, 1090735660aSJohnny Huang { 1100735660aSJohnny Huang INFO("gd25q256c", 0xc84019, 0, 64 * 1024, 512, 1110735660aSJohnny Huang SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 1120735660aSJohnny Huang SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) 1130735660aSJohnny Huang }, 11497989e54SChin-Ting Kuo { 11597989e54SChin-Ting Kuo INFO("gd25b512m", 0xc8471a, 0, 64 * 1024, 1024, 11697989e54SChin-Ting Kuo SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 11797989e54SChin-Ting Kuo SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) 11897989e54SChin-Ting Kuo }, 11997989e54SChin-Ting Kuo { 12097989e54SChin-Ting Kuo INFO("gd55b512m", 0xc8401a, 0, 64 * 1024, 1024, 12197989e54SChin-Ting Kuo SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 12297989e54SChin-Ting Kuo SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) 12397989e54SChin-Ting Kuo }, 12497989e54SChin-Ting Kuo { 125c916075fSChin-Ting Kuo INFO("gd55b01gf", 0xc8401b, 0, 64 * 1024, 2048, 126c916075fSChin-Ting Kuo SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 127c916075fSChin-Ting Kuo SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) 128c916075fSChin-Ting Kuo }, 129c916075fSChin-Ting Kuo { 130c916075fSChin-Ting Kuo INFO("gd55b02gf", 0xc8401c, 0, 64 * 1024, 4096, 131c916075fSChin-Ting Kuo SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 132c916075fSChin-Ting Kuo SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) 133c916075fSChin-Ting Kuo }, 134c916075fSChin-Ting Kuo { 13597989e54SChin-Ting Kuo INFO("gd55b01ge", 0xc8471b, 0, 64 * 1024, 2048, 136080c9802SChin-Ting Kuo SECT_4K | SPI_NOR_QUAD_READ | 13797989e54SChin-Ting Kuo SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) 13897989e54SChin-Ting Kuo }, 139734f8860SChin-Ting Kuo { 140734f8860SChin-Ting Kuo INFO("gd55b02ge", 0xc8471c, 0, 64 * 1024, 4096, 141080c9802SChin-Ting Kuo SECT_4K | SPI_NOR_QUAD_READ | 142734f8860SChin-Ting Kuo SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) 143734f8860SChin-Ting Kuo }, 144778572d7SVignesh R #endif 145778572d7SVignesh R #ifdef CONFIG_SPI_FLASH_ISSI /* ISSI */ 146778572d7SVignesh R /* ISSI */ 147778572d7SVignesh R { INFO("is25lq040b", 0x9d4013, 0, 64 * 1024, 8, 148778572d7SVignesh R SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 149778572d7SVignesh R { INFO("is25lp032", 0x9d6016, 0, 64 * 1024, 64, 0) }, 150778572d7SVignesh R { INFO("is25lp064", 0x9d6017, 0, 64 * 1024, 128, 0) }, 151778572d7SVignesh R { INFO("is25lp128", 0x9d6018, 0, 64 * 1024, 256, 152778572d7SVignesh R SECT_4K | SPI_NOR_DUAL_READ) }, 153778572d7SVignesh R { INFO("is25lp256", 0x9d6019, 0, 64 * 1024, 512, 154778572d7SVignesh R SECT_4K | SPI_NOR_DUAL_READ) }, 15500554b9bSChin-Ting Kuo { INFO("is25lp512m", 0x9d601a, 0, 64 * 1024, 1024, 15600554b9bSChin-Ting Kuo SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 157734f8860SChin-Ting Kuo { INFO("is25lp01g", 0x9d601b, 0, 64 * 1024, 2048, 158734f8860SChin-Ting Kuo SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 159778572d7SVignesh R { INFO("is25wp032", 0x9d7016, 0, 64 * 1024, 64, 160778572d7SVignesh R SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 161778572d7SVignesh R { INFO("is25wp064", 0x9d7017, 0, 64 * 1024, 128, 162778572d7SVignesh R SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 163778572d7SVignesh R { INFO("is25wp128", 0x9d7018, 0, 64 * 1024, 256, 164778572d7SVignesh R SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 165778572d7SVignesh R #endif 166778572d7SVignesh R #ifdef CONFIG_SPI_FLASH_MACRONIX /* MACRONIX */ 167778572d7SVignesh R /* Macronix */ 168778572d7SVignesh R { INFO("mx25l2005a", 0xc22012, 0, 64 * 1024, 4, SECT_4K) }, 169778572d7SVignesh R { INFO("mx25l4005a", 0xc22013, 0, 64 * 1024, 8, SECT_4K) }, 170778572d7SVignesh R { INFO("mx25l8005", 0xc22014, 0, 64 * 1024, 16, 0) }, 171778572d7SVignesh R { INFO("mx25l1606e", 0xc22015, 0, 64 * 1024, 32, SECT_4K) }, 172778572d7SVignesh R { INFO("mx25l3205d", 0xc22016, 0, 64 * 1024, 64, SECT_4K) }, 173778572d7SVignesh R { INFO("mx25l6405d", 0xc22017, 0, 64 * 1024, 128, SECT_4K) }, 174778572d7SVignesh R { INFO("mx25u2033e", 0xc22532, 0, 64 * 1024, 4, SECT_4K) }, 175778572d7SVignesh R { INFO("mx25u1635e", 0xc22535, 0, 64 * 1024, 32, SECT_4K) }, 176778572d7SVignesh R { INFO("mx25u6435f", 0xc22537, 0, 64 * 1024, 128, SECT_4K) }, 177778572d7SVignesh R { INFO("mx25l12805d", 0xc22018, 0, 64 * 1024, 256, 0) }, 178778572d7SVignesh R { INFO("mx25l12855e", 0xc22618, 0, 64 * 1024, 256, 0) }, 179778572d7SVignesh R { INFO("mx25l25635e", 0xc22019, 0, 64 * 1024, 512, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 180778572d7SVignesh R { INFO("mx25u25635f", 0xc22539, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_4B_OPCODES) }, 181778572d7SVignesh R { INFO("mx25l25655e", 0xc22619, 0, 64 * 1024, 512, 0) }, 182778572d7SVignesh R { INFO("mx66l51235l", 0xc2201a, 0, 64 * 1024, 1024, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, 183778572d7SVignesh R { INFO("mx66u51235f", 0xc2253a, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, 184778572d7SVignesh R { INFO("mx66l1g45g", 0xc2201b, 0, 64 * 1024, 2048, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 185c770759cSChin-Ting Kuo { INFO("mx66l2g45g", 0xc2201c, 0, 64 * 1024, 4096, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 186778572d7SVignesh R { INFO("mx25l1633e", 0xc22415, 0, 64 * 1024, 32, SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES | SECT_4K) }, 187778572d7SVignesh R #endif 188778572d7SVignesh R 189778572d7SVignesh R #ifdef CONFIG_SPI_FLASH_STMICRO /* STMICRO */ 190778572d7SVignesh R /* Micron */ 191778572d7SVignesh R { INFO("n25q016a", 0x20bb15, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_QUAD_READ) }, 192778572d7SVignesh R { INFO("n25q032", 0x20ba16, 0, 64 * 1024, 64, SPI_NOR_QUAD_READ) }, 193778572d7SVignesh R { INFO("n25q032a", 0x20bb16, 0, 64 * 1024, 64, SPI_NOR_QUAD_READ) }, 194778572d7SVignesh R { INFO("n25q064", 0x20ba17, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_QUAD_READ) }, 195778572d7SVignesh R { INFO("n25q064a", 0x20bb17, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_QUAD_READ) }, 196778572d7SVignesh R { INFO("n25q128a11", 0x20bb18, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_QUAD_READ) }, 197778572d7SVignesh R { INFO("n25q128a13", 0x20ba18, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_QUAD_READ) }, 198778572d7SVignesh R { INFO("n25q256a", 0x20ba19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, 199778572d7SVignesh R { INFO("n25q256ax1", 0x20bb19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, 200778572d7SVignesh R { INFO("n25q512a", 0x20bb20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, 201778572d7SVignesh R { INFO("n25q512ax3", 0x20ba20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, 202778572d7SVignesh R { INFO("n25q00", 0x20ba21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) }, 203734f8860SChin-Ting Kuo { INFO("mt25ql02g", 0x20ba22, 0, 64 * 1024, 4096, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) }, 204778572d7SVignesh R { INFO("n25q00a", 0x20bb21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) }, 205778572d7SVignesh R { INFO("mt25qu02g", 0x20bb22, 0, 64 * 1024, 4096, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) }, 206778572d7SVignesh R #endif 207778572d7SVignesh R #ifdef CONFIG_SPI_FLASH_SPANSION /* SPANSION */ 208778572d7SVignesh R /* Spansion/Cypress -- single (large) sector size only, at least 209778572d7SVignesh R * for the chips listed here (without boot sectors). 210778572d7SVignesh R */ 211778572d7SVignesh R { INFO("s25sl032p", 0x010215, 0x4d00, 64 * 1024, 64, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 212778572d7SVignesh R { INFO("s25sl064p", 0x010216, 0x4d00, 64 * 1024, 128, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 213778572d7SVignesh R { INFO("s25fl256s0", 0x010219, 0x4d00, 256 * 1024, 128, USE_CLSR) }, 214778572d7SVignesh R { INFO("s25fl256s1", 0x010219, 0x4d01, 64 * 1024, 512, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) }, 215778572d7SVignesh R { INFO6("s25fl512s", 0x010220, 0x4d0081, 256 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) }, 216778572d7SVignesh R { INFO("s25fl512s_256k", 0x010220, 0x4d00, 256 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) }, 217778572d7SVignesh R { INFO("s25fl512s_64k", 0x010220, 0x4d01, 64 * 1024, 1024, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) }, 218778572d7SVignesh R { INFO("s25fl512s_512k", 0x010220, 0x4f00, 256 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) }, 219778572d7SVignesh R { INFO("s25sl12800", 0x012018, 0x0300, 256 * 1024, 64, 0) }, 220778572d7SVignesh R { INFO("s25sl12801", 0x012018, 0x0301, 64 * 1024, 256, 0) }, 221778572d7SVignesh R { INFO6("s25fl128s", 0x012018, 0x4d0180, 64 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) }, 222778572d7SVignesh R { INFO("s25fl129p0", 0x012018, 0x4d00, 256 * 1024, 64, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) }, 223778572d7SVignesh R { INFO("s25fl129p1", 0x012018, 0x4d01, 64 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) }, 224778572d7SVignesh R { INFO("s25sl008a", 0x010213, 0, 64 * 1024, 16, 0) }, 225778572d7SVignesh R { INFO("s25sl016a", 0x010214, 0, 64 * 1024, 32, 0) }, 226778572d7SVignesh R { INFO("s25sl032a", 0x010215, 0, 64 * 1024, 64, 0) }, 227778572d7SVignesh R { INFO("s25sl064a", 0x010216, 0, 64 * 1024, 128, 0) }, 228778572d7SVignesh R { INFO("s25fl116k", 0x014015, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 229778572d7SVignesh R { INFO("s25fl164k", 0x014017, 0, 64 * 1024, 128, SECT_4K) }, 230778572d7SVignesh R { INFO("s25fl208k", 0x014014, 0, 64 * 1024, 16, SECT_4K | SPI_NOR_DUAL_READ) }, 231778572d7SVignesh R { INFO("s25fl128l", 0x016018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, 2320e0a1e5bSJohnny Huang { INFO("s25fl256l", 0x016019, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, 233cd800046SChin-Ting Kuo /* S25HL/HS-T (Semper Flash with Quad SPI) Family has overlaid 4KB 234cd800046SChin-Ting Kuo * sectors at top and/or bottom, depending on the device configuration. 235cd800046SChin-Ting Kuo * To support this, an erase hook makes overlaid sectors appear as 236cd800046SChin-Ting Kuo * uniform sectors. 237cd800046SChin-Ting Kuo */ 238cd800046SChin-Ting Kuo { INFO6("s25hl256t", 0x342a19, 0x0f0390, 256 * 1024, 128, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES | USE_CLSR) }, 239cd800046SChin-Ting Kuo { INFO6("s25hl512t", 0x342a1a, 0x0f0390, 256 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES | USE_CLSR) }, 240cd800046SChin-Ting Kuo { INFO6("s25hl01gt", 0x342a1b, 0x0f0390, 256 * 1024, 512, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES | USE_CLSR) }, 241cd800046SChin-Ting Kuo { INFO6("s25hs256t", 0x342b19, 0x0f0390, 256 * 1024, 128, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES | USE_CLSR) }, 242cd800046SChin-Ting Kuo { INFO6("s25hs512t", 0x342b1a, 0x0f0390, 256 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES | USE_CLSR) }, 243cd800046SChin-Ting Kuo { INFO6("s25hs01gt", 0x342b1b, 0x0f0390, 256 * 1024, 512, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES | USE_CLSR) }, 244778572d7SVignesh R #endif 245778572d7SVignesh R #ifdef CONFIG_SPI_FLASH_SST /* SST */ 246778572d7SVignesh R /* SST -- large erase sizes are "overlays", "sectors" are 4K */ 247778572d7SVignesh R { INFO("sst25vf040b", 0xbf258d, 0, 64 * 1024, 8, SECT_4K | SST_WRITE) }, 248778572d7SVignesh R { INFO("sst25vf080b", 0xbf258e, 0, 64 * 1024, 16, SECT_4K | SST_WRITE) }, 249778572d7SVignesh R { INFO("sst25vf016b", 0xbf2541, 0, 64 * 1024, 32, SECT_4K | SST_WRITE) }, 250778572d7SVignesh R { INFO("sst25vf032b", 0xbf254a, 0, 64 * 1024, 64, SECT_4K | SST_WRITE) }, 251778572d7SVignesh R { INFO("sst25vf064c", 0xbf254b, 0, 64 * 1024, 128, SECT_4K) }, 252778572d7SVignesh R { INFO("sst25wf512", 0xbf2501, 0, 64 * 1024, 1, SECT_4K | SST_WRITE) }, 253778572d7SVignesh R { INFO("sst25wf010", 0xbf2502, 0, 64 * 1024, 2, SECT_4K | SST_WRITE) }, 254778572d7SVignesh R { INFO("sst25wf020", 0xbf2503, 0, 64 * 1024, 4, SECT_4K | SST_WRITE) }, 255778572d7SVignesh R { INFO("sst25wf020a", 0x621612, 0, 64 * 1024, 4, SECT_4K) }, 256778572d7SVignesh R { INFO("sst25wf040b", 0x621613, 0, 64 * 1024, 8, SECT_4K) }, 257778572d7SVignesh R { INFO("sst25wf040", 0xbf2504, 0, 64 * 1024, 8, SECT_4K | SST_WRITE) }, 258778572d7SVignesh R { INFO("sst25wf080", 0xbf2505, 0, 64 * 1024, 16, SECT_4K | SST_WRITE) }, 259778572d7SVignesh R { INFO("sst26vf064b", 0xbf2643, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 260778572d7SVignesh R { INFO("sst26wf016", 0xbf2651, 0, 64 * 1024, 32, SECT_4K) }, 261778572d7SVignesh R { INFO("sst26wf032", 0xbf2622, 0, 64 * 1024, 64, SECT_4K) }, 262778572d7SVignesh R { INFO("sst26wf064", 0xbf2643, 0, 64 * 1024, 128, SECT_4K) }, 263778572d7SVignesh R #endif 264778572d7SVignesh R #ifdef CONFIG_SPI_FLASH_STMICRO /* STMICRO */ 265778572d7SVignesh R /* ST Microelectronics -- newer production may have feature updates */ 266778572d7SVignesh R { INFO("m25p10", 0x202011, 0, 32 * 1024, 4, 0) }, 267778572d7SVignesh R { INFO("m25p20", 0x202012, 0, 64 * 1024, 4, 0) }, 268778572d7SVignesh R { INFO("m25p40", 0x202013, 0, 64 * 1024, 8, 0) }, 269778572d7SVignesh R { INFO("m25p80", 0x202014, 0, 64 * 1024, 16, 0) }, 270778572d7SVignesh R { INFO("m25p16", 0x202015, 0, 64 * 1024, 32, 0) }, 271778572d7SVignesh R { INFO("m25p32", 0x202016, 0, 64 * 1024, 64, 0) }, 272778572d7SVignesh R { INFO("m25p64", 0x202017, 0, 64 * 1024, 128, 0) }, 273778572d7SVignesh R { INFO("m25p128", 0x202018, 0, 256 * 1024, 64, 0) }, 274778572d7SVignesh R { INFO("m25pe16", 0x208015, 0, 64 * 1024, 32, SECT_4K) }, 275778572d7SVignesh R { INFO("m25px16", 0x207115, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 276778572d7SVignesh R { INFO("m25px64", 0x207117, 0, 64 * 1024, 128, 0) }, 277778572d7SVignesh R #endif 278778572d7SVignesh R #ifdef CONFIG_SPI_FLASH_WINBOND /* WINBOND */ 279778572d7SVignesh R /* Winbond -- w25x "blocks" are 64K, "sectors" are 4KiB */ 280778572d7SVignesh R { INFO("w25p80", 0xef2014, 0x0, 64 * 1024, 16, 0) }, 281778572d7SVignesh R { INFO("w25p16", 0xef2015, 0x0, 64 * 1024, 32, 0) }, 282778572d7SVignesh R { INFO("w25p32", 0xef2016, 0x0, 64 * 1024, 64, 0) }, 283778572d7SVignesh R { INFO("w25x05", 0xef3010, 0, 64 * 1024, 1, SECT_4K) }, 284778572d7SVignesh R { INFO("w25x40", 0xef3013, 0, 64 * 1024, 8, SECT_4K) }, 285778572d7SVignesh R { INFO("w25x16", 0xef3015, 0, 64 * 1024, 32, SECT_4K) }, 286778572d7SVignesh R { 287778572d7SVignesh R INFO("w25q16dw", 0xef6015, 0, 64 * 1024, 32, 288778572d7SVignesh R SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 289778572d7SVignesh R SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) 290778572d7SVignesh R }, 291778572d7SVignesh R { INFO("w25x32", 0xef3016, 0, 64 * 1024, 64, SECT_4K) }, 292778572d7SVignesh R { INFO("w25q20cl", 0xef4012, 0, 64 * 1024, 4, SECT_4K) }, 293778572d7SVignesh R { INFO("w25q20bw", 0xef5012, 0, 64 * 1024, 4, SECT_4K) }, 294778572d7SVignesh R { INFO("w25q20ew", 0xef6012, 0, 64 * 1024, 4, SECT_4K) }, 295778572d7SVignesh R { INFO("w25q32", 0xef4016, 0, 64 * 1024, 64, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 296778572d7SVignesh R { 297778572d7SVignesh R INFO("w25q32dw", 0xef6016, 0, 64 * 1024, 64, 298778572d7SVignesh R SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 299778572d7SVignesh R SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) 300778572d7SVignesh R }, 301778572d7SVignesh R { 302778572d7SVignesh R INFO("w25q32jv", 0xef7016, 0, 64 * 1024, 64, 303778572d7SVignesh R SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 304778572d7SVignesh R SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) 305778572d7SVignesh R }, 306778572d7SVignesh R { INFO("w25x64", 0xef3017, 0, 64 * 1024, 128, SECT_4K) }, 307778572d7SVignesh R { 308778572d7SVignesh R INFO("w25q64dw", 0xef6017, 0, 64 * 1024, 128, 309778572d7SVignesh R SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 310778572d7SVignesh R SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) 311778572d7SVignesh R }, 312778572d7SVignesh R { 313778572d7SVignesh R INFO("w25q64jv", 0xef7017, 0, 64 * 1024, 128, 314778572d7SVignesh R SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 315778572d7SVignesh R SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) 316778572d7SVignesh R }, 317778572d7SVignesh R { 318778572d7SVignesh R INFO("w25q128fw", 0xef6018, 0, 64 * 1024, 256, 319778572d7SVignesh R SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 320778572d7SVignesh R SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) 321778572d7SVignesh R }, 322778572d7SVignesh R { 323778572d7SVignesh R INFO("w25q128jv", 0xef7018, 0, 64 * 1024, 256, 324778572d7SVignesh R SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 325778572d7SVignesh R SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) 326778572d7SVignesh R }, 327778572d7SVignesh R { 328778572d7SVignesh R INFO("w25q256fw", 0xef6019, 0, 64 * 1024, 512, 329778572d7SVignesh R SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 330778572d7SVignesh R SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) 331778572d7SVignesh R }, 332778572d7SVignesh R { 333de79270aSChin-Ting Kuo INFO("w25q256fm", 0xef7019, 0, 64 * 1024, 512, 334778572d7SVignesh R SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 335778572d7SVignesh R SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) 336778572d7SVignesh R }, 337b981181dSJohnny Huang { 338b981181dSJohnny Huang INFO("w25q512jv", 0xef4020, 0, 64 * 1024, 1024, 339b981181dSJohnny Huang SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 340b981181dSJohnny Huang SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) 341b981181dSJohnny Huang }, 34207b728f9SChin-Ting Kuo { 343e79c9eb2SChin-Ting Kuo INFO("w25q512jvfm", 0xef7020, 0, 64 * 1024, 1024, 344e79c9eb2SChin-Ting Kuo SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 345e79c9eb2SChin-Ting Kuo SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) 346e79c9eb2SChin-Ting Kuo }, 347e79c9eb2SChin-Ting Kuo { 348*02fb6009SJae Hyun Yoo INFO("w25q512nwq", 0xef6020, 0, 64 * 1024, 1024, 349*02fb6009SJae Hyun Yoo SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 350*02fb6009SJae Hyun Yoo SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) 351*02fb6009SJae Hyun Yoo }, 352*02fb6009SJae Hyun Yoo { 353*02fb6009SJae Hyun Yoo INFO("w25q512nwm", 0xef8020, 0, 64 * 1024, 1024, 354*02fb6009SJae Hyun Yoo SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 355*02fb6009SJae Hyun Yoo SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) 356*02fb6009SJae Hyun Yoo }, 357*02fb6009SJae Hyun Yoo { 35807b728f9SChin-Ting Kuo INFO("w25q01jv", 0xef4021, 0, 64 * 1024, 2048, 35907b728f9SChin-Ting Kuo SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 36007b728f9SChin-Ting Kuo SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) 36107b728f9SChin-Ting Kuo }, 362de79270aSChin-Ting Kuo { 363c770759cSChin-Ting Kuo INFO("w25q02jv", 0xef7022, 0, 64 * 1024, 4096, 364c770759cSChin-Ting Kuo SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 365c770759cSChin-Ting Kuo SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) 366c770759cSChin-Ting Kuo }, 367c770759cSChin-Ting Kuo { 368de79270aSChin-Ting Kuo INFO("w25q01jvfim", 0xef7021, 0, 64 * 1024, 2048, 369de79270aSChin-Ting Kuo SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 370de79270aSChin-Ting Kuo SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) 371de79270aSChin-Ting Kuo }, 372778572d7SVignesh R { INFO("w25q80", 0xef5014, 0, 64 * 1024, 16, SECT_4K) }, 373778572d7SVignesh R { INFO("w25q80bl", 0xef4014, 0, 64 * 1024, 16, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 374778572d7SVignesh R { INFO("w25q16cl", 0xef4015, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 375778572d7SVignesh R { INFO("w25q64cv", 0xef4017, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 376778572d7SVignesh R { INFO("w25q128", 0xef4018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 377778572d7SVignesh R { INFO("w25q256", 0xef4019, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 378977fa7aeSryan_chen { INFO("w25m512jv", 0xef7119, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_QUAD_READ | SPI_NOR_DUAL_READ) }, 379778572d7SVignesh R #endif 380778572d7SVignesh R #ifdef CONFIG_SPI_FLASH_XMC 381778572d7SVignesh R /* XMC (Wuhan Xinxin Semiconductor Manufacturing Corp.) */ 382778572d7SVignesh R { INFO("XM25QH64A", 0x207017, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 383778572d7SVignesh R { INFO("XM25QH128A", 0x207018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, 384778572d7SVignesh R #endif 385778572d7SVignesh R { }, 386778572d7SVignesh R }; 387