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Searched +full:400 +full:khz (Results 1 – 25 of 240) sorted by relevance

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/openbmc/u-boot/drivers/i2c/
H A Daspeed_i2c_global.c30 * I2CG10[23:16] base clk3 for Standard-mode (100Khz) min tBuf 4.7us
31 * 0x3c : 100.8Khz : 3.225Mhz : 4.96us
32 * 0x3d : 99.2Khz : 3.174Mhz : 5.04us
33 * 0x3e : 97.65Khz : 3.125Mhz : 5.12us
34 * 0x40 : 97.75Khz : 3.03Mhz : 5.28us
35 * 0x41 : 99.5Khz : 2.98Mhz : 5.36us (default)
36 * I2CG10[15:8] base clk2 for Fast-mode (400Khz) min tBuf 1.3us
37 * 0x12 : 400Khz : 10Mhz : 1.6us
H A Dsandbox_i2c.c71 * For testing, don't allow writing above 100KHz for writes and in sandbox_i2c_xfer()
72 * 400KHz for reads. in sandbox_i2c_xfer()
/openbmc/linux/drivers/video/fbdev/core/
H A Dmodedb.c38 /* 640x400 @ 70 Hz, 31.5 kHz hsync */
39 { NULL, 70, 640, 400, 39721, 40, 24, 39, 9, 96, 2, 0,
42 /* 640x480 @ 60 Hz, 31.5 kHz hsync */
46 /* 800x600 @ 56 Hz, 35.15 kHz hsync */
50 /* 1024x768 @ 87 Hz interlaced, 35.5 kHz hsync */
54 /* 640x400 @ 85 Hz, 37.86 kHz hsync */
55 { NULL, 85, 640, 400, 31746, 96, 32, 41, 1, 64, 3,
58 /* 640x480 @ 72 Hz, 36.5 kHz hsync */
62 /* 640x480 @ 75 Hz, 37.50 kHz hsync */
66 /* 800x600 @ 60 Hz, 37.8 kHz hsync */
[all …]
/openbmc/linux/drivers/i2c/
H A Di2c-core-acpi.c347 * These Silead touchscreen controllers only work at 400KHz, for
348 * some reason they do not work at 100KHz. On some devices the ACPI
350 * of 100KHz, testing has shown that these other devices work fine
351 * at 400KHz (as can be expected of any recent i2c hw) so we force
352 * the speed of the bus to 400 KHz if a Silead device is present.
360 * When a 400KHz freq is used on this model of ELAN touchpad in Linux,
363 * V15 G4) ACPI tables specify a 400KHz frequency for this device and
364 * some I2C busses (e.g, Designware I2C) default to a 400KHz freq,
365 * force the speed to 100KHz as a workaround.
371 * a 400KHz frequency. The root cause of the issue is not known.
/openbmc/linux/Documentation/i2c/busses/
H A Di2c-ismt.rst21 Specify the bus speed in kHz.
27 80 kHz
28 100 kHz
29 400 kHz
30 1000 kHz
/openbmc/u-boot/arch/arm/mach-omap2/
H A Dvc.c51 * @speed_khz: I2C buspeed in KHz
60 if (speed_khz > 400) { in omap_vc_init()
61 puts("higher speed requested - throttle to 400Khz\n"); in omap_vc_init()
62 speed_khz = 400; in omap_vc_init()
/openbmc/linux/drivers/i3c/master/mipi-i3c-hci/
H A Dxfer_mode_rate.h53 #define XFERRATE_I3C_SDR_FM_FMP 0x05 /* 400 KHz / 1 MHz */
57 #define XFERRATE_I2C_FM 0x00 /* 400 KHz */
/openbmc/linux/Documentation/devicetree/bindings/sound/
H A Dti,j721e-cpb-audio.yaml18 In order to support 48KHz and 44.1KHz family of sampling rates the parent
19 clock for AUDIO_REFCLK2 needs to be changed between PLL4 (for 48KHz) and
20 PLL15 (for 44.1KHz). The same PLLs are used for McASP10's AUXCLK clock via
24 48KHz family:
28 44.1KHz family:
33 48KHz family:
85 - description: Parent for CPB_McASP auxclk (for 48KHz)
86 - description: Parent for CPB_McASP auxclk (for 44.1KHz)
88 - description: Parent for CPB_SCKI clock (for 48KHz)
89 - description: Parent for CPB_SCKI clock (for 44.1KHz)
[all …]
H A Dti,j721e-cpb-ivi-audio.yaml23 In order to support 48KHz and 44.1KHz family of sampling rates the parent clock
24 for AUDIO_REFCLK0 needs to be changed between PLL4 (for 48KHz) and PLL15 (for
25 44.1KHz). The same PLLs are used for McASP0's AUXCLK clock via different
30 Clocking setup for 48KHz family:
37 Clocking setup for 44.1KHz family:
76 - description: Parent for CPB_McASP auxclk (for 48KHz)
77 - description: Parent for CPB_McASP auxclk (for 44.1KHz)
79 - description: Parent for CPB_SCKI clock (for 48KHz)
80 - description: Parent for CPB_SCKI clock (for 44.1KHz)
82 - description: Parent for IVI_McASP auxclk (for 48KHz)
[all …]
/openbmc/linux/Documentation/hwmon/
H A Dmcp3021.rst36 compatible interface. Standard (100 kHz) and Fast (400 kHz) I2C modes are
/openbmc/linux/arch/arm/boot/dts/allwinner/
H A Dsun5i-reference-design-tablet.dtsi88 * The gsl1680 is rated at 400KHz and it will not work reliable at
89 * 100KHz, this has been confirmed on multiple different q8 tablets.
90 * All other devices on this bus are also rated for 400KHz.
/openbmc/linux/drivers/clk/spear/
H A Dspear1340_clock.c167 {.mode = 0, .m = 0x64, .n = 0x06, .p = 0x1}, /* vco 800, pll 400 MHz */
179 {.mode = 0, .m = 0xC8, .n = 0x06, .p = 0x2}, /* vco 1600, pll 400 MHz */
190 {.div = 0x04D1B}, /* for vco1div2 = 400 MHz */
202 * 250, 332, 400 or 500 MHz considering different possibilites of input
208 * 400 200 100 0x04000
209 * 400 250 125 0x03333
210 * 400 332 166 0x0268D
211 * 400 400 200 0x02000
216 * 500 400 200 0x02800
222 * 600 400 200 0x03000
[all …]
/openbmc/linux/drivers/i2c/busses/
H A Di2c-stm32.h19 STM32_I2C_SPEED_STANDARD, /* 100 kHz */
20 STM32_I2C_SPEED_FAST, /* 400 kHz */
H A Di2c-designware-common.c197 * Only standard mode at 100kHz, fast mode at 400kHz, in i2c_dw_validate_speed()
206 "%d Hz is unsupported, only 100kHz, 400kHz, 1MHz and 3.4MHz are supported\n", in i2c_dw_validate_speed()
463 * transfer supported by the driver (for 400KHz this is in __i2c_dw_disable()
492 * transfer supported by the driver (for 400KHz this is in __i2c_dw_disable()
H A Di2c-stm32f4.c161 * To reach 100 kHz, the parent clk frequency should be between in stm32f4_i2c_set_periph_clk_freq()
173 * To be as close as possible to 400 kHz, the parent clk in stm32f4_i2c_set_periph_clk_freq()
234 * So to reach 100 kHz, we have: in stm32f4_i2c_set_speed_mode()
235 * CCR = I2C parent rate / (100 kHz * 2) in stm32f4_i2c_set_speed_mode()
240 * t_scl_high + t_scl_low = 10000 ns so 100 kHz is reached in stm32f4_i2c_set_speed_mode()
250 * frequencies we are not able to reach 400 kHz. in stm32f4_i2c_set_speed_mode()
254 * So, CCR = I2C parent rate / (400 kHz * 3) in stm32f4_i2c_set_speed_mode()
260 * t_scl_high + t_scl_low = 2500 ns so 400 kHz is reached in stm32f4_i2c_set_speed_mode()
H A Di2c-ismt.c147 #define ISMT_SPGT_SPD_80K 0x00 /* 80 kHz */
148 #define ISMT_SPGT_SPD_100K (0x1 << 30) /* 100 kHz */
149 #define ISMT_SPGT_SPD_400K (0x2U << 30) /* 400 kHz */
198 MODULE_PARM_DESC(bus_speed, "Bus Speed in kHz (0 = BIOS default)");
747 dev_dbg(dev, "Setting SMBus clock to 80 kHz\n"); in ismt_hw_init()
753 dev_dbg(dev, "Setting SMBus clock to 100 kHz\n"); in ismt_hw_init()
758 case 400: in ismt_hw_init()
759 dev_dbg(dev, "Setting SMBus clock to 400 kHz\n"); in ismt_hw_init()
765 dev_dbg(dev, "Setting SMBus clock to 1000 kHz\n"); in ismt_hw_init()
771 dev_warn(dev, "Invalid SMBus clock speed, only 0, 80, 100, 400, and 1000 are valid\n"); in ismt_hw_init()
[all …]
/openbmc/linux/Documentation/devicetree/bindings/regulator/
H A Drichtek,rt6245-regulator.yaml63 Buck switch frequency selection. Each respective value means 400KHz,
64 800KHz, 1200KHz. If this property is missing then keep in chip default.
/openbmc/u-boot/arch/arm/dts/
H A Dsun5i-reference-design-tablet.dtsi89 * The gsl1680 is rated at 400KHz and it will not work reliable at
90 * 100KHz, this has been confirmed on multiple different q8 tablets.
91 * All other devices on this bus are also rated for 400KHz.
/openbmc/u-boot/drivers/mmc/
H A Drockchip_dw_mmc.c85 priv->minmax[0] = 400000; /* 400 kHz */ in rockchip_dwmmc_ofdata_to_platdata()
115 priv->minmax[0] = 400000; /* 400 kHz */ in rockchip_dwmmc_probe()
/openbmc/u-boot/doc/device-tree-bindings/mmc/
H A Dmsm_sdhci.txt14 - clock-frequency: Frequency of SD/eMMC bus (default 400 kHz)
/openbmc/linux/Documentation/devicetree/bindings/i2c/
H A Di2c-lpc2k.txt13 absence of this property the default value is used (100 kHz).
16 i2c0: i2c@400a1000 {
H A Dopencores,i2c-ocores.yaml45 frequency is fixed at 100 KHz.
109 clock-frequency = <400000>; /* i2c bus frequency 400 KHz */
/openbmc/linux/sound/firewire/fireface/
H A Dff-protocol-latter.c62 // 0x00: 32.0 kHz
63 // 0x01: 44.1 kHz
64 // 0x02: 48.0 kHz
65 // 0x04: 64.0 kHz
66 // 0x05: 88.2 kHz
67 // 0x06: 96.0 kHz
68 // 0x08: 128.0 kHz
69 // 0x09: 176.4 kHz
70 // 0x0a: 192.0 kHz
269 // IEEE 1394a (400 Mbps), Analog 1-12 and AES are available in latter_begin_session()
[all …]
/openbmc/linux/sound/soc/codecs/
H A Dmax9877.c32 0, 7, TLV_DB_SCALE_ITEM(-7900, 400, 1),
51 "1176KHz",
52 "1100KHz",
53 "700KHz",
/openbmc/linux/drivers/media/radio/
H A Dlm7000.h29 freq /= 400; /* Convert to 25 kHz units */ in lm7000_set_freq()

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