Searched +full:0 +full:xfffffd00 (Results 1 – 21 of 21) sorted by relevance
66 reg = <0xfffffd00 0x10>;
20 #define ATMEL_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */26 #define ATMEL_ID_USART0 6 /* USART 0 */31 #define ATMEL_ID_TWI0 11 /* TWI 0 */34 #define ATMEL_ID_SSC0 14 /* Serial Synchronous Controller 0 */36 #define ATMEL_ID_TC0 16 /* Timer Counter 0 */50 #define ATMEL_BASE_TCB0 0xfffa000051 #define ATMEL_BASE_TC0 0xfffa000052 #define ATMEL_BASE_TC1 0xfffa004053 #define ATMEL_BASE_TC2 0xfffa008054 #define ATMEL_BASE_MCI 0xfffa4000[all …]
18 #define ATMEL_ID_USART0 6 /* USART 0 */26 #define ATMEL_ID_SSC0 14 /* Synch. Serial Controller 0 */29 #define ATMEL_ID_TC0 17 /* Timer Counter 0 */45 #define ATMEL_USB_HOST_BASE 0x0030000047 #define ATMEL_BASE_TC 0xFFFA000048 #define ATMEL_BASE_UDP 0xFFFB000049 #define ATMEL_BASE_MCI 0xFFFB400050 #define ATMEL_BASE_TWI 0xFFFB800051 #define ATMEL_BASE_EMAC 0xFFFBC00052 #define ATMEL_BASE_USART 0xFFFC0000 /* 4x 0x4000 Offset */[all …]
23 #define ATMEL_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */29 #define ATMEL_ID_USART0 6 /* USART 0 */34 #define ATMEL_ID_TWI0 11 /* Two-Wire Interface 0 */35 #define ATMEL_ID_SPI0 12 /* Serial Peripheral Interface 0 */37 #define ATMEL_ID_SSC0 14 /* Serial Synchronous Controller 0 */40 #define ATMEL_ID_TC0 17 /* Timer Counter 0 */53 #define ATMEL_BASE_TCB0 0xfffa000054 #define ATMEL_BASE_TC0 0xfffa000055 #define ATMEL_BASE_TC1 0xfffa004056 #define ATMEL_BASE_TC2 0xfffa0080[all …]
19 #define ATMEL_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */26 #define ATMEL_ID_USART0 7 /* USART 0 */29 #define ATMEL_ID_MCI0 10 /* Multimedia Card Interface 0 */33 #define ATMEL_ID_SPI0 14 /* Serial Peripheral Interface 0 */35 #define ATMEL_ID_SSC0 16 /* Serial Synchronous Controller 0 */38 #define ATMEL_ID_TCB 19 /* Timer Counter 0, 1 and 2 */55 #define ATMEL_BASE_UDP 0xfff7800056 #define ATMEL_BASE_TCB0 0xfff7c00057 #define ATMEL_BASE_TC0 0xfff7c00058 #define ATMEL_BASE_TC1 0xfff7c040[all …]
17 #define ATMEL_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */24 #define ATMEL_ID_USART0 7 /* USART 0 */28 #define ATMEL_ID_MCI0 11 /* High Speed Multimedia Card Interface 0 */29 #define ATMEL_ID_TWI0 12 /* Two-Wire Interface 0 */31 #define ATMEL_ID_SPI0 14 /* Serial Peripheral Interface 0 */33 #define ATMEL_ID_SSC0 16 /* Synchronous Serial Controller 0 */35 #define ATMEL_ID_TCB 18 /* Timer Counter 0, 1, 2, 3, 4 and 5 */53 #define ATMEL_BASE_UDPHS 0xfff7800054 #define ATMEL_BASE_TC0 0xfff7c00055 #define ATMEL_BASE_TC1 0xfff7c040[all …]
23 #define ATMEL_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */29 #define ATMEL_ID_USART0 6 /* USART 0 */34 #define ATMEL_ID_TWI0 11 /* Two-Wire Interface 0 */35 #define ATMEL_ID_SPI0 12 /* Serial Peripheral Interface 0 */37 #define ATMEL_ID_SSC0 14 /* Serial Synchronous Controller 0 */40 #define ATMEL_ID_TC0 17 /* Timer Counter 0 */44 #define ATMEL_ID_EMAC0 21 /* Ethernet 0 */59 #define ATMEL_BASE_TCB0 0xfffa000060 #define ATMEL_BASE_TC0 0xfffa000061 #define ATMEL_BASE_TC1 0xfffa0040[all …]
38 #size-cells = <0>;40 cpu@0 {43 reg = <0>;49 reg = <0x20000000 0x08000000>;55 #clock-cells = <0>;56 clock-frequency = <0>;61 #clock-cells = <0>;62 clock-frequency = <0>;68 reg = <0x00300000 0x28000>;71 ranges = <0 0x00300000 0x28000>;[all …]
44 #size-cells = <0>;46 cpu@0 {49 reg = <0>;55 reg = <0x20000000 0x04000000>;61 #clock-cells = <0>;62 clock-frequency = <0>;67 #clock-cells = <0>;68 clock-frequency = <0>;74 reg = <0x00200000 0x4000>;77 ranges = <0 0x00200000 0x4000>;[all …]
43 #size-cells = <0>;45 cpu@0 {48 reg = <0>;54 reg = <0x20000000 0x04000000>;60 #clock-cells = <0>;61 clock-frequency = <0>;66 #clock-cells = <0>;67 clock-frequency = <0>;72 #clock-cells = <0>;79 reg = <0x00300000 0x10000>;[all …]
41 #size-cells = <0>;43 cpu@0 {46 reg = <0>;52 reg = <0x20000000 0x04000000>;58 #clock-cells = <0>;59 clock-frequency = <0>;64 #clock-cells = <0>;65 clock-frequency = <0>;70 #clock-cells = <0>;77 reg = <0x002ff000 0x2000>;[all …]
40 #size-cells = <0>;42 cpu@0 {45 reg = <0>;51 reg = <0x20000000 0x08000000>;57 #clock-cells = <0>;58 clock-frequency = <0>;63 #clock-cells = <0>;64 clock-frequency = <0>;70 reg = <0x00300000 0x14000>;73 ranges = <0 0x00300000 0x14000>;[all …]
46 #size-cells = <0>;48 cpu@0 {51 reg = <0>;57 reg = <0x70000000 0x10000000>;63 #clock-cells = <0>;64 clock-frequency = <0>;69 #clock-cells = <0>;70 clock-frequency = <0>;75 #clock-cells = <0>;82 reg = <0x00300000 0x10000>;[all …]
44 reg = <0x20000000 0x08000000>;50 #clock-cells = <0>;51 clock-frequency = <0>;56 #clock-cells = <0>;57 clock-frequency = <0>;63 reg = <0x00300000 0x28000>;75 reg = <0x00500000 0x100000>;82 fb0: fb@0x00600000 {84 reg = <0x00600000 0x1000>;87 pinctrl-0 = <&pinctrl_fb>;[all …]
48 reg = <0x20000000 0x04000000>;54 #clock-cells = <0>;55 clock-frequency = <0>;60 #clock-cells = <0>;61 clock-frequency = <0>;66 #clock-cells = <0>;73 reg = <0x00300000 0x10000>;85 reg = <0x00500000 0x1000>;88 pinctrl-0 = <&pinctrl_fb>;98 reg = <0x40000000 0x10000000>,[all …]
46 reg = <0x20000000 0x08000000>;52 #clock-cells = <0>;53 clock-frequency = <0>;58 #clock-cells = <0>;59 clock-frequency = <0>;65 reg = <0x00300000 0x14000>;70 reg = <0x00500000 0x4000>;91 reg = <0xfffff000 0x200>;97 reg = <0xfffffc00 0x100>;101 #size-cells = <0>;[all …]
47 reg = <0x20000000 0x04000000>;53 #clock-cells = <0>;54 clock-frequency = <0>;59 #clock-cells = <0>;60 clock-frequency = <0>;65 #clock-cells = <0>;72 reg = <0x002ff000 0x2000>;93 reg = <0xfffff000 0x200>;99 reg = <0xffffea00 0x200>;104 reg = <0xfffffc00 0x100>;[all …]
51 reg = <0x70000000 0x10000000>;57 #clock-cells = <0>;58 clock-frequency = <0>;63 #clock-cells = <0>;64 clock-frequency = <0>;69 #clock-cells = <0>;76 reg = <0x00300000 0x10000>;97 reg = <0xfffff000 0x200>;103 reg = <0xffffe400 0x200>;110 reg = <0xffffe600 0x200>;[all …]
27 * 0xFFFFF0xx -- System Control34 #define SCR_ADDR 0xfffff00037 #define SCR_WDTH8 0x01 /* 8-Bit Width Select */38 #define SCR_DMAP 0x04 /* Double Map */39 #define SCR_SO 0x08 /* Supervisor Only */40 #define SCR_BETEN 0x10 /* Bus-Error Time-Out Enable */41 #define SCR_PRV 0x20 /* Privilege Violation */42 #define SCR_WPV 0x40 /* Write Protect Violation */43 #define SCR_BETO 0x80 /* Bus-Error TimeOut */48 #define MRR_ADDR 0xfffff004[all …]
29 * 0xFFFFF0xx -- System Control36 #define SCR_ADDR 0xfffff00039 #define SCR_WDTH8 0x01 /* 8-Bit Width Select */40 #define SCR_DMAP 0x04 /* Double Map */41 #define SCR_SO 0x08 /* Supervisor Only */42 #define SCR_BETEN 0x10 /* Bus-Error Time-Out Enable */43 #define SCR_PRV 0x20 /* Privilege Violation */44 #define SCR_WPV 0x40 /* Write Protect Violation */45 #define SCR_BETO 0x80 /* Bus-Error TimeOut */50 #define MRR_ADDR 0xfffff004[all …]
42 * All register has 2 addresses: in 0xff000000 - 0xffffffff (P4 address) and43 * in 0x1f000000 - 0x1fffffff (area 7 address)45 #define SH7750_P4_BASE 0xff000000 /* Accessible only in privileged mode */46 #define SH7750_A7_BASE 0x1f000000 /* Accessible only using TLB */56 #define SH7750_PTEH_REGOFS 0x000000 /* offset */59 #define SH7750_PTEH_VPN 0xfffffd00 /* Virtual page number */61 #define SH7750_PTEH_ASID 0x000000ff /* Address space identifier */62 #define SH7750_PTEH_ASID_S 065 #define SH7750_PTEL_REGOFS 0x000004 /* offset */68 #define SH7750_PTEL_PPN 0x1ffffc00 /* Physical page number */[all …]